Primitive: 2-to-1 Look-Up Table Multiplexer with General Output
Introduction
This design element is a two input multiplexer which, in combination with two LUT6 elements will let you create any 7-input function, an 8-to-1 multiplexer, or other logic functions up to 12-bits wide. Local outputs of the LUT6 element are connected to the I0 and I1 inputs of the MUXF7. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1.
The O output is a general interconnect.
Logic Table
Inputs | Outputs | ||
---|---|---|---|
S | I0 | I1 | O |
0 | I0 | X | I0 |
1 | X | I1 | I1 |
X | 0 | 0 | 0 |
X | 1 | 1 | 1 |
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
O | Output | 1 | Output of MUX to general routing. |
I0 | Input | 1 | Input (tie to LUT6 LO out). |
I1 | Input | 1 | Input (tie to LUT6 LO out). |
S | Input | 1 | Input select to MUX. |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP Catalog | No |
Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MUXF7: CLB MUX to tie two LUT6's together with general output
-- 7 Series
-- Xilinx HDL Language Template, version 2021.2
MUXF7_inst : MUXF7
port map (
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie to LUT6 O6 pin)
I1 => I1, -- Input (tie to LUT6 O6 pin)
S => S -- Input select to MUX
);
-- End of MUXF7_inst instantiation
Verilog Instantiation Template
// MUXF7: CLB MUX to tie two LUT6's together with general output
// 7 Series
// Xilinx HDL Language Template, version 2021.2
MUXF7 MUXF7_inst (
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie to LUT6 O6 pin)
.I1(I1), // Input (tie to LUT6 O6 pin)
.S(S) // Input select to MUX
);
// End of MUXF7_inst instantiation
Related Information
- See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).