Primitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT)
Introduction
This element is a runtime, dynamically reconfigurable, 5-input look-up table (LUT) that enables the changing of the logical function of the LUT during circuit operation. Using the CDI pin, a new INIT value can be synchronously shifted in serially to change the logical function. The O6 output pin produces the logical output function, based on the current INIT value loaded into the LUT and the currently selected I0-I4 input pins. Optionally, you can use the O5 output in combination with the O6 output to create two individual 4-input functions sharing the same inputs or a 5-input function and a 4-input function that uses a subset of the 5-input logic (see the following tables). This component occupies one of the four LUT6 components within a Slice-M.
To cascade this element, connect the CDO pin from each element to the CDI input of the next element. This will allow a single serial chain of data (32-bits per LUT) to reconfigure multiple LUTs.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
O6 | Output | 1 | 5-LUT output. |
O5 | Output | 1 | 4-LUT output. |
I0, I1, I2, I3, I4 | Input | 1 | LUT inputs. |
CDO | Output | 1 | Reconfiguration data cascaded output (optionally connect to the CDI input of a subsequent LUT). |
CDI | Input | 1 | Reconfiguration data serial input. |
CLK | Input | 1 | Reconfiguration clock. |
CE | Input | 1 | Active-High reconfiguration clock enable. |
Design Entry Method
Instantiation | Recommended |
Inference | No |
IP Catalog | No |
Macro support | No |
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Connect the CLK input to the clock source used to supply the reconfiguration data.
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Connect the CDI input to the source of the reconfiguration data.
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Connect the CE pin to the active-High logic if you need to enable/disable LUT reconfiguration.
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Connect the I4-I0 pins to the source inputs to the logic equation. The logic function is output on O6 and O5.
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To cascade this element, connect the CDO pin from each element to the CDI input of the next element to allow a single serial chain of data to reconfigure multiple LUTs.
The INIT attribute should be placed on this design element to specify the initial logical function of the LUT. A new INIT can be loaded into the LUT any time during circuit operation by shifting in 32-bits per LUT in the chain, representing the new INIT value. Disregard the O6 and O5 output data until all 32-bits of new INIT data has been clocked into the LUT. The logical function of the LUT changes as new INIT data is shifted into it. Data should be shifted in MSB (INIT[31]) first and LSB (INIT[0]) last.
In order to understand the O6 and O5 logical value based on the current INIT, see the following table.
I4 I3 I2 I1 I0 | O6 Value | O5 Value |
---|---|---|
1 1 1 1 1 | INIT[31] | INIT[15] |
1 1 1 1 0 | INIT[30] | INIT[14] |
. . . | . . . | . . . |
1 0 0 0 1 | INIT[17] | INIT[1] |
1 0 0 0 0 | INIT[16] | INIT[0] |
0 1 1 1 1 | INIT[15] | INIT[15] |
0 1 1 1 0 | INIT[14] | INIT[14] |
. . . | . . . | . . . |
0 0 0 0 1 | INIT[1] | INIT[1] |
0 0 0 0 0 | INIT[0] | INIT[0] |
For instance, the INIT value of FFFF8000 would represent the following logical equations:
- O6 = I4 or (I3 and I2 and I1 and I0)
- O5 = I3 and I2 and I1 and I0
To use these elements as two, 4-input LUTs with the same inputs but different functions, tie the I4 signal to a logical one. The INIT[31:16] values apply to the logical values of the O6 output and INIT [15:0] apply to the logical values of the O5 output.
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
INIT | HEX | Any 32-bit value | All zeros | Specifies the initial logical expression of this element. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- CFGLUT5: Reconfigurable 5-input LUT (Mapped to SliceM LUT6)
-- 7 Series
-- Xilinx HDL Language Template, version 2021.2
CFGLUT5_inst : CFGLUT5
generic map (
INT => X"00000000")
port map (
CDO => CDO, -- Reconfiguration cascade output
O5 => O5, -- 4-LUT output
O6 => O6, -- 5-LUT output
CDI => CDI, -- Reconfiguration data input
CE => CE, -- Reconfiguration enable input
CLK => CLK, -- Clock input
I0 => I0, -- Logic data input
I1 => I1, -- Logic data input
I2 => I2, -- Logic data input
I3 => I3, -- Logic data input
I4 => I4 -- Logic data input
);
-- End of CFGLUT5_inst instantiation
Verilog Instantiation Template
// CFGLUT5: Reconfigurable 5-input LUT (Mapped to a SliceM LUT6)
// 7 Series
// Xilinx HDL Language Template, version 2021.2
CFGLUT5 #(
.INIT(32'h00000000) // Specify initial LUT contents
) CFGLUT5_inst (
.CDO(CDO), // Reconfiguration cascade output
.O5(O5), // 4-LUT output
.O6(O6), // 5-LUT output
.CDI(CDI), // Reconfiguration data input
.CE(CE), // Reconfiguration enable input
.CLK(CLK), // Clock input
.I0(I0), // Logic data input
.I1(I1), // Logic data input
.I2(I2), // Logic data input
.I3(I3), // Logic data input
.I4(I4) // Logic data input
);
// End of CFGLUT5_inst instantiation
Related Information
- See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).