Primitive: D Flip-Flop with Clock Enable and Synchronous Reset
Introduction
This design element is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Low on the Low-to-High clock (C) transition. The data on the (D) input is loaded into the flip-flop when R is Low and CE is High during the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. Power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_E2 symbol.
Logic Table
Inputs | Outputs | |||
---|---|---|---|---|
R | CE | D | C | Q |
1 | X | X | ↑ | 0 |
0 | 0 | X | X | No Change |
0 | 1 | D | ↑ | D |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP Catalog | No |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
INIT | BINARY | 0, 1 | 0 | Sets the initial value of Q output after configuration. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
-- 7 Series
-- Xilinx HDL Language Template, version 2021.2
FDRE_inst : FDRE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
R => R, -- Synchronous reset input
D => D -- Data input
);
-- End of FDRE_inst instantiation
Verilog Instantiation Template
// FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
// Clock Enable (posedge clk).
// 7 Series
// Xilinx HDL Language Template, version 2021.2
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(Q), // 1-bit Data output
.C(C), // 1-bit Clock input
.CE(CE), // 1-bit Clock enable input
.R(R), // 1-bit Synchronous reset input
.D(D) // 1-bit Data input
);
// End of FDRE_inst instantiation
Related Information
- See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).