COUNTER_LOAD_MACRO - 2021.2 English

Macro: Loadable Counter

Introduction

COUNTER_LOAD_MACRO simplifies the instantiation of the DSP48 block when used as dynamic loading up/down counter. It features parameterizable output width and count by values that ease the integration of the DSP48 block into HDL.

Port Descriptions

Port	Direction	Width	Function
Q	Output	Variable, see WIDTH_DATA attribute.	Counter output.
CE	Input	1	Clock Enable.
CLK	Input	1	Clock.
LOAD	Input	Variable, see WIDTH_DATA attribute.	When asserted, loads the counter from LOAD_DATA (two-clock latency).
LOAD_DATA	Input	Variable, see WIDTH_DATA attribute.	In a DSP slice, asserting the LOAD pin will force this data into the P register with a latency of 2 clocks.
DIRECTION	Input	1	High for Up and Low for Down (two-clock latency)
RST	Input	1	Synchronous Reset

Design Entry Method

This unimacro is a parameterizable version of the primitive, and can be instantiated only.

Instantiation	Yes
Inference	No
IP Catalog	No
Macro support	Recommended

Available Attributes

Attribute	Type	Allowed Values	Default	Description
DEVICE	STRING	"7SERIES"	"7SERIES"	Target hardware architecture.
COUNT_BY	HEX	Any 48-bit value.	000000000001	Count by n; takes precedence over WIDTH_DATA.
WIDTH_DATA	INTEGER	1-48	48	Specifies counter width.

VHDL Instantiation Template

Unless they already exist, copy the following four statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;


-- COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
--                     7 Series
-- Xilinx HDL Language Template, version 2021.2

COUNTER_LOAD_MACRO_inst : COUNTER_LOAD_MACRO
generic map (
   COUNT_BY => X"000000000001", -- Count by value
   DEVICE => "7SERIES",         -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
   WIDTH_DATA => 48)            -- Counter output bus width, 1-48
port map (
   Q => Q,                 -- Counter ouput, width determined by WIDTH_DATA generic
   CLK => CLK,             -- 1-bit clock input
   CE => CE,               -- 1-bit clock enable input
   DIRECTION => DIRECTION, -- 1-bit up/down count direction input, high is count up
   LOAD => LOAD,           -- 1-bit active high load input
   LOAD_DATA => LOAD_DATA, -- Counter load data, width determined by WIDTH_DATA generic
   RST => RST              -- 1-bit active high synchronous reset
);
-- End of COUNTER_LOAD_MACRO_inst instantiation

Verilog Instantiation Template


// COUNTER_LOAD_MACRO: Loadable variable counter implemented in a DSP48E
//                     7 Series
// Xilinx HDL Language Template, version 2021.2

COUNTER_LOAD_MACRO #(
   .COUNT_BY(48'h000000000001), // Count by value
   .DEVICE("7SERIES"), // Target Device: "7SERIES"
   .WIDTH_DATA(48)     // Counter output bus width, 1-48
) COUNTER_LOAD_MACRO_inst (
   .Q(Q),                 // Counter output, width determined by WIDTH_DATA parameter
   .CLK(CLK),             // 1-bit clock input
   .CE(CE),               // 1-bit clock enable input
   .DIRECTION(DIRECTION), // 1-bit up/down count direction input, high is count up
   .LOAD(LOAD),           // 1-bit active high load input
   .LOAD_DATA(LOAD_DATA), // Counter load data, width determined by WIDTH_DATA parameter
   .RST(RST)              // 1-bit active high synchronous reset
);

// End of COUNTER_LOAD_MACRO_inst instantiation