Parameterized Macro: AXI Stream FIFO
- MACRO_GROUP: XPM
- MACRO_SUBGROUP: XPM_FIFO
Introduction
This macro is used to instantiate AXI Stream FIFO.
AXI Stream FIFO is derived from the XPM_FIFO_SYNC and XPM_FIFO_ASYNC. The AXI Stream protocol uses a two-way valid and ready handshake mechanism. The information source uses the valid signal to show when valid data or control information is available on the channel. The information destination uses the ready signal to show when it can accept the data.
Timing Diagrams
In the timing diagram above, the information source generates a valid signal to indicate when data is available. The destination generates a ready signal to indicate that it can accept data, and transfer occurs only when both the valid and ready signals are High.
Because the AXI Stream FIFO is derived from XPM_FIFO_SYNC and XPM_FIFO_ASYNC, much of the behavior is common between them. The ready signal is generated based on availability of space in the FIFO and is held high to allow writes to the FIFO. The ready signal is pulled Low only when there is no space in the FIFO left to perform additional writes. The valid signal is generated based on availability of data in the FIFO and is held High to allow reads to be performed from the FIFO. The valid signal is pulled Low only when there is no data available to be read from the FIFO. The information signals are mapped to the din and dout bus of Native interface FIFOs. The width of the AXI FIFO is determined by concatenating all of the information signals of the AXI interface. The information signals include all AXI signals except for the valid and ready handshake signals.
The AXI Stream FIFO operates only in First-Word Fall-Through mode. The First-Word Fall-Through (FWFT) feature provides the ability to look ahead to the next word available from the FIFO without issuing a read operation. When data is available in the FIFO, the first word falls through the FIFO and appears automatically on the output data bus.
Port Descriptions
Port | Direction | Width | Domain | Sense | Handling if Unused | Function |
---|---|---|---|---|---|---|
almost_empty_axis | Output | 1 | m_aclk | LEVEL_HIGH | DoNotCare | Almost Empty : When asserted, this signal indicates that only one more read can be performed before the FIFO goes to empty. |
almost_full_axis | Output | 1 | s_aclk | LEVEL_HIGH | DoNotCare | Almost Full: When asserted, this signal indicates that only one more write can be performed before the FIFO is full. |
dbiterr_axis | Output | 1 | m_aclk | LEVEL_HIGH | DoNotCare | Double Bit Error- Indicates that the ECC decoder detected a double-bit error and data in the FIFO core is corrupted. |
injectdbiterr_axis | Input | 1 | s_aclk | LEVEL_HIGH | 0 | Double Bit Error Injection- Injects a double bit error if the ECC feature is used. |
injectsbiterr_axis | Input | 1 | s_aclk | LEVEL_HIGH | 0 | Single Bit Error Injection- Injects a single bit error if the ECC feature is used. |
m_aclk | Input | 1 | NA | EDGE_RISING | Active | Master Interface Clock: All signals on master interface are sampled on the rising edge of this clock. |
m_axis_tdata | Output | TDATA_WIDTH | m_aclk | NA | Active | TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes. |
m_axis_tdest | Output | TDEST_WIDTH | m_aclk | NA | Active | TDEST: Provides routing information for the data stream. |
m_axis_tid | Output | TID_WIDTH | m_aclk | NA | Active | TID: The data stream identifier that indicates different streams of data. |
m_axis_tkeep | Output | TDATA_WIDTH / 8 | m_aclk | NA | Active | TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed
as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes
and can be removed from the data stream. For a 64-bit DATA, bit 0 corresponds to the least significant byte
on DATA, and bit 7 corresponds to the most significant byte. For example:
|
m_axis_tlast | Output | 1 | m_aclk | LEVEL_HIGH | Active | TLAST: Indicates the boundary of a packet. |
m_axis_tready | Input | 1 | m_aclk | LEVEL_HIGH | Active | TREADY: Indicates that the slave can accept a transfer in the current cycle. |
m_axis_tstrb | Output | TDATA_WIDTH / 8 | m_aclk | NA | Active | TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed
as a data byte or a position byte. For a 64-bit DATA, bit 0 corresponds to the least significant byte on
DATA, and bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant
byte. For example:
|
m_axis_tuser | Output | TUSER_WIDTH | m_aclk | NA | Active | TUSER: The user-defined sideband information that can be transmitted alongside the data stream. |
m_axis_tvalid | Output | 1 | m_aclk | LEVEL_HIGH | Active | TVALID: Indicates that the master is driving a valid transfer.
|
prog_empty_axis | Output | 1 | m_aclk | LEVEL_HIGH | DoNotCare |
Programmable Empty- This signal is asserted when the number of words in the FIFO is less than or equal to the programmable empty threshold value. It is de-asserted when the number of words in the FIFO exceeds the programmable empty threshold value. |
prog_full_axis | Output | 1 | s_aclk | LEVEL_HIGH | DoNotCare |
Programmable Full: This signal is asserted when the number of words in the FIFO is greater than or equal to the programmable full threshold value. It is de-asserted when the number of words in the FIFO is less than the programmable full threshold value. |
rd_data_count_axis | Output | RD_DATA_COUNT_WIDTH | m_aclk | NA | DoNotCare | Read Data Count- This bus indicates the number of words available for reading in the FIFO. |
s_aclk | Input | 1 | NA | EDGE_RISING | Active | Slave Interface Clock: All signals on slave interface are sampled on the rising edge of this clock. |
s_aresetn | Input | 1 | NA | LEVEL_LOW | Active | Active low asynchronous reset. |
s_axis_tdata | Input | TDATA_WIDTH | s_aclk | NA | Active | TDATA: The primary payload that is used to provide the data that is passing across the interface. The width of the data payload is an integer number of bytes. |
s_axis_tdest | Input | TDEST_WIDTH | s_aclk | NA | Active | TDEST: Provides routing information for the data stream. |
s_axis_tid | Input | TID_WIDTH | s_aclk | NA | Active | TID: The data stream identifier that indicates different streams of data. |
s_axis_tkeep | Input | TDATA_WIDTH / 8 | s_aclk | NA | Active | TKEEP: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed
as part of the data stream. Associated bytes that have the TKEEP byte qualifier deasserted are null bytes
and can be removed from the data stream. For a 64-bit DATA, bit 0 corresponds to the least significant byte
on DATA, and bit 7 corresponds to the most significant byte. For example:
|
s_axis_tlast | Input | 1 | s_aclk | LEVEL_HIGH | Active | TLAST: Indicates the boundary of a packet. |
s_axis_tready | Output | 1 | s_aclk | LEVEL_HIGH | Active | TREADY: Indicates that the slave can accept a transfer in the current cycle. |
s_axis_tstrb | Input | TDATA_WIDTH / 8 | s_aclk | NA | Active | TSTRB: The byte qualifier that indicates whether the content of the associated byte of TDATA is processed
as a data byte or a position byte. For a 64-bit DATA, bit 0 corresponds to the least significant byte on
DATA, and bit 0 corresponds to the least significant byte on DATA, and bit 7 corresponds to the most significant
byte. For example:
|
s_axis_tuser | Input | TUSER_WIDTH | s_aclk | NA | Active | TUSER: The user-defined sideband information that can be transmitted alongside the data stream. |
s_axis_tvalid | Input | 1 | s_aclk | LEVEL_HIGH | Active | TVALID: Indicates that the master is driving a valid transfer.
|
sbiterr_axis | Output | 1 | m_aclk | LEVEL_HIGH | DoNotCare | Single Bit Error- Indicates that the ECC decoder detected and fixed a single-bit error. |
wr_data_count_axis | Output | WR_DATA_COUNT_WIDTH | s_aclk | NA | DoNotCare | Write Data Count: This bus indicates the number of words written into the FIFO. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP and IP Integrator Catalog | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
CASCADE_HEIGHT | DECIMAL | 0 to 64 | 0 |
0- No Cascade Height, Allow Vivado Synthesis to choose. 1 or more - Vivado Synthesis sets the specified value as Cascade Height. |
CDC_SYNC_STAGES | DECIMAL | 2 to 8 | 2 |
Specifies the number of synchronization stages on the CDC path. Applicable only if CLOCKING_MODE = "independent_clock" |
CLOCKING_MODE | STRING | "common_clock", "independent_clock" | "common_clock" | Designate whether AXI Stream FIFO is clocked with a common clock or with independent clocks-
|
ECC_MODE | STRING | "no_ecc", "en_ecc" | "no_ecc" |
|
FIFO_DEPTH | DECIMAL | 16 to 4194304 | 2048 | Defines the AXI Stream FIFO Write Depth, must be power of two NOTE: The maximum FIFO size (width x depth) is limited to 150-Megabits. |
FIFO_MEMORY_TYPE | STRING | "auto", "block", "distributed", "ultra" | "auto" | Designate the fifo memory primitive (resource type) to use-
|
PACKET_FIFO | STRING | "false", "true" | "false" |
|
PROG_EMPTY_THRESH | DECIMAL | 5 to 4194301 | 10 |
Specifies the minimum number of read words in the FIFO at or below which prog_empty is asserted.
|
PROG_FULL_THRESH | DECIMAL | 5 to 4194301 | 10 |
Specifies the maximum number of write words in the FIFO at or above which prog_full is asserted.
|
RD_DATA_COUNT_WIDTH | DECIMAL | 1 to 23 | 1 | Specifies the width of rd_data_count_axis. To reflect the correct value, the width should be log2(FIFO_DEPTH)+1. |
RELATED_CLOCKS | DECIMAL | 0 to 1 | 0 |
Specifies if the s_aclk and m_aclk are related having the same source but different clock ratios. Applicable only if CLOCKING_MODE = "independent_clock" |
SIM_ASSERT_CHK | DECIMAL | 0 to 1 | 0 |
0- Disable simulation message reporting. Messages related to potential misuse will not be reported. 1- Enable simulation message reporting. Messages related to potential misuse will be reported. |
TDATA_WIDTH | DECIMAL | 8 to 2048 | 32 | Defines the width of the TDATA port, s_axis_tdata and m_axis_tdata NOTE: The maximum FIFO size (width x depth) is limited to 150-Megabits. |
TDEST_WIDTH | DECIMAL | 1 to 32 | 1 | Defines the width of the TDEST port, s_axis_tdest and m_axis_tdest |
TID_WIDTH | DECIMAL | 1 to 32 | 1 | Defines the width of the ID port, s_axis_tid and m_axis_tid |
TUSER_WIDTH | DECIMAL | 1 to 4086 | 1 | Defines the width of the TUSER port, s_axis_tuser and m_axis_tuser |
USE_ADV_FEATURES | STRING | String | "1000" |
Enables almost_empty_axis, rd_data_count_axis, prog_empty_axis, almost_full_axis, wr_data_count_axis, prog_full_axis sideband signals.
|
WR_DATA_COUNT_WIDTH | DECIMAL | 1 to 23 | 1 | Specifies the width of wr_data_count_axis. To reflect the correct value, the width should be log2(FIFO_DEPTH)+1. |
VHDL Instantiation Template
Library xpm;
use xpm.vcomponents.all;
-- xpm_fifo_axis: AXI Stream FIFO
-- Xilinx Parameterized Macro, version 2021.2
xpm_fifo_axis_inst : xpm_fifo_axis
generic map (
CASCADE_HEIGHT => 0, -- DECIMAL
CDC_SYNC_STAGES => 2, -- DECIMAL
CLOCKING_MODE => "common_clock", -- String
ECC_MODE => "no_ecc", -- String
FIFO_DEPTH => 2048, -- DECIMAL
FIFO_MEMORY_TYPE => "auto", -- String
PACKET_FIFO => "false", -- String
PROG_EMPTY_THRESH => 10, -- DECIMAL
PROG_FULL_THRESH => 10, -- DECIMAL
RD_DATA_COUNT_WIDTH => 1, -- DECIMAL
RELATED_CLOCKS => 0, -- DECIMAL
SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
TDATA_WIDTH => 32, -- DECIMAL
TDEST_WIDTH => 1, -- DECIMAL
TID_WIDTH => 1, -- DECIMAL
TUSER_WIDTH => 1, -- DECIMAL
USE_ADV_FEATURES => "1000", -- String
WR_DATA_COUNT_WIDTH => 1 -- DECIMAL
)
port map (
almost_empty_axis => almost_empty_axis, -- 1-bit output: Almost Empty : When asserted, this signal
-- indicates that only one more read can be performed before
-- the FIFO goes to empty.
almost_full_axis => almost_full_axis, -- 1-bit output: Almost Full: When asserted, this signal
-- indicates that only one more write can be performed before
-- the FIFO is full.
dbiterr_axis => dbiterr_axis, -- 1-bit output: Double Bit Error- Indicates that the ECC
-- decoder detected a double-bit error and data in the FIFO
-- core is corrupted.
m_axis_tdata => m_axis_tdata, -- TDATA_WIDTH-bit output: TDATA: The primary payload that is
-- used to provide the data that is passing across the
-- interface. The width of the data payload is an integer
-- number of bytes.
m_axis_tdest => m_axis_tdest, -- TDEST_WIDTH-bit output: TDEST: Provides routing information
-- for the data stream.
m_axis_tid => m_axis_tid, -- TID_WIDTH-bit output: TID: The data stream identifier that
-- indicates different streams of data.
m_axis_tkeep => m_axis_tkeep, -- TDATA_WIDTH/8-bit output: TKEEP: The byte qualifier that
-- indicates whether the content of the associated byte of
-- TDATA is processed as part of the data stream. Associated
-- bytes that have the TKEEP byte qualifier deasserted are null
-- bytes and can be removed from the data stream. For a 64-bit
-- DATA, bit 0 corresponds to the least significant byte on
-- DATA, and bit 7 corresponds to the most significant byte.
-- For example: KEEP[0] = 1b, DATA[7:0] is not a NULL byte
-- KEEP[7] = 0b, DATA[63:56] is a NULL byte
m_axis_tlast => m_axis_tlast, -- 1-bit output: TLAST: Indicates the boundary of a packet.
m_axis_tstrb => m_axis_tstrb, -- TDATA_WIDTH/8-bit output: TSTRB: The byte qualifier that
-- indicates whether the content of the associated byte of
-- TDATA is processed as a data byte or a position byte. For a
-- 64-bit DATA, bit 0 corresponds to the least significant byte
-- on DATA, and bit 0 corresponds to the least significant byte
-- on DATA, and bit 7 corresponds to the most significant byte.
-- For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] =
-- 0b, DATA[63:56] is not valid
m_axis_tuser => m_axis_tuser, -- TUSER_WIDTH-bit output: TUSER: The user-defined sideband
-- information that can be transmitted alongside the data
-- stream.
m_axis_tvalid => m_axis_tvalid, -- 1-bit output: TVALID: Indicates that the master is driving a
-- valid transfer. A transfer takes place when both TVALID and
-- TREADY are asserted
prog_empty_axis => prog_empty_axis, -- 1-bit output: Programmable Empty- This signal is asserted
-- when the number of words in the FIFO is less than or equal
-- to the programmable empty threshold value. It is de-asserted
-- when the number of words in the FIFO exceeds the
-- programmable empty threshold value.
prog_full_axis => prog_full_axis, -- 1-bit output: Programmable Full: This signal is asserted
-- when the number of words in the FIFO is greater than or
-- equal to the programmable full threshold value. It is
-- de-asserted when the number of words in the FIFO is less
-- than the programmable full threshold value.
rd_data_count_axis => rd_data_count_axis, -- RD_DATA_COUNT_WIDTH-bit output: Read Data Count- This bus
-- indicates the number of words available for reading in the
-- FIFO.
s_axis_tready => s_axis_tready, -- 1-bit output: TREADY: Indicates that the slave can accept a
-- transfer in the current cycle.
sbiterr_axis => sbiterr_axis, -- 1-bit output: Single Bit Error- Indicates that the ECC
-- decoder detected and fixed a single-bit error.
wr_data_count_axis => wr_data_count_axis, -- WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus
-- indicates the number of words written into the FIFO.
injectdbiterr_axis => injectdbiterr_axis, -- 1-bit input: Double Bit Error Injection- Injects a double
-- bit error if the ECC feature is used.
injectsbiterr_axis => injectsbiterr_axis, -- 1-bit input: Single Bit Error Injection- Injects a single
-- bit error if the ECC feature is used.
m_aclk => m_aclk, -- 1-bit input: Master Interface Clock: All signals on master
-- interface are sampled on the rising edge of this clock.
m_axis_tready => m_axis_tready, -- 1-bit input: TREADY: Indicates that the slave can accept a
-- transfer in the current cycle.
s_aclk => s_aclk, -- 1-bit input: Slave Interface Clock: All signals on slave
-- interface are sampled on the rising edge of this clock.
s_aresetn => s_aresetn, -- 1-bit input: Active low asynchronous reset.
s_axis_tdata => s_axis_tdata, -- TDATA_WIDTH-bit input: TDATA: The primary payload that is
-- used to provide the data that is passing across the
-- interface. The width of the data payload is an integer
-- number of bytes.
s_axis_tdest => s_axis_tdest, -- TDEST_WIDTH-bit input: TDEST: Provides routing information
-- for the data stream.
s_axis_tid => s_axis_tid, -- TID_WIDTH-bit input: TID: The data stream identifier that
-- indicates different streams of data.
s_axis_tkeep => s_axis_tkeep, -- TDATA_WIDTH/8-bit input: TKEEP: The byte qualifier that
-- indicates whether the content of the associated byte of
-- TDATA is processed as part of the data stream. Associated
-- bytes that have the TKEEP byte qualifier deasserted are null
-- bytes and can be removed from the data stream. For a 64-bit
-- DATA, bit 0 corresponds to the least significant byte on
-- DATA, and bit 7 corresponds to the most significant byte.
-- For example: KEEP[0] = 1b, DATA[7:0] is not a NULL byte
-- KEEP[7] = 0b, DATA[63:56] is a NULL byte
s_axis_tlast => s_axis_tlast, -- 1-bit input: TLAST: Indicates the boundary of a packet.
s_axis_tstrb => s_axis_tstrb, -- TDATA_WIDTH/8-bit input: TSTRB: The byte qualifier that
-- indicates whether the content of the associated byte of
-- TDATA is processed as a data byte or a position byte. For a
-- 64-bit DATA, bit 0 corresponds to the least significant byte
-- on DATA, and bit 0 corresponds to the least significant byte
-- on DATA, and bit 7 corresponds to the most significant byte.
-- For example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] =
-- 0b, DATA[63:56] is not valid
s_axis_tuser => s_axis_tuser, -- TUSER_WIDTH-bit input: TUSER: The user-defined sideband
-- information that can be transmitted alongside the data
-- stream.
s_axis_tvalid => s_axis_tvalid -- 1-bit input: TVALID: Indicates that the master is driving a
-- valid transfer. A transfer takes place when both TVALID and
-- TREADY are asserted
);
-- End of xpm_fifo_axis_inst instantiation
Verilog Instantiation Template
// xpm_fifo_axis: AXI Stream FIFO
// Xilinx Parameterized Macro, version 2021.2
xpm_fifo_axis #(
.CASCADE_HEIGHT(0), // DECIMAL
.CDC_SYNC_STAGES(2), // DECIMAL
.CLOCKING_MODE("common_clock"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_DEPTH(2048), // DECIMAL
.FIFO_MEMORY_TYPE("auto"), // String
.PACKET_FIFO("false"), // String
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(1), // DECIMAL
.RELATED_CLOCKS(0), // DECIMAL
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.TDATA_WIDTH(32), // DECIMAL
.TDEST_WIDTH(1), // DECIMAL
.TID_WIDTH(1), // DECIMAL
.TUSER_WIDTH(1), // DECIMAL
.USE_ADV_FEATURES("1000"), // String
.WR_DATA_COUNT_WIDTH(1) // DECIMAL
)
xpm_fifo_axis_inst (
.almost_empty_axis(almost_empty_axis), // 1-bit output: Almost Empty : When asserted, this signal
// indicates that only one more read can be performed before the
// FIFO goes to empty.
.almost_full_axis(almost_full_axis), // 1-bit output: Almost Full: When asserted, this signal
// indicates that only one more write can be performed before
// the FIFO is full.
.dbiterr_axis(dbiterr_axis), // 1-bit output: Double Bit Error- Indicates that the ECC
// decoder detected a double-bit error and data in the FIFO core
// is corrupted.
.m_axis_tdata(m_axis_tdata), // TDATA_WIDTH-bit output: TDATA: The primary payload that is
// used to provide the data that is passing across the
// interface. The width of the data payload is an integer number
// of bytes.
.m_axis_tdest(m_axis_tdest), // TDEST_WIDTH-bit output: TDEST: Provides routing information
// for the data stream.
.m_axis_tid(m_axis_tid), // TID_WIDTH-bit output: TID: The data stream identifier that
// indicates different streams of data.
.m_axis_tkeep(m_axis_tkeep), // TDATA_WIDTH/8-bit output: TKEEP: The byte qualifier that
// indicates whether the content of the associated byte of TDATA
// is processed as part of the data stream. Associated bytes
// that have the TKEEP byte qualifier deasserted are null bytes
// and can be removed from the data stream. For a 64-bit DATA,
// bit 0 corresponds to the least significant byte on DATA, and
// bit 7 corresponds to the most significant byte. For example:
// KEEP[0] = 1b, DATA[7:0] is not a NULL byte KEEP[7] = 0b,
// DATA[63:56] is a NULL byte
.m_axis_tlast(m_axis_tlast), // 1-bit output: TLAST: Indicates the boundary of a packet.
.m_axis_tstrb(m_axis_tstrb), // TDATA_WIDTH/8-bit output: TSTRB: The byte qualifier that
// indicates whether the content of the associated byte of TDATA
// is processed as a data byte or a position byte. For a 64-bit
// DATA, bit 0 corresponds to the least significant byte on
// DATA, and bit 0 corresponds to the least significant byte on
// DATA, and bit 7 corresponds to the most significant byte. For
// example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b,
// DATA[63:56] is not valid
.m_axis_tuser(m_axis_tuser), // TUSER_WIDTH-bit output: TUSER: The user-defined sideband
// information that can be transmitted alongside the data
// stream.
.m_axis_tvalid(m_axis_tvalid), // 1-bit output: TVALID: Indicates that the master is driving a
// valid transfer. A transfer takes place when both TVALID and
// TREADY are asserted
.prog_empty_axis(prog_empty_axis), // 1-bit output: Programmable Empty- This signal is asserted
// when the number of words in the FIFO is less than or equal to
// the programmable empty threshold value. It is de-asserted
// when the number of words in the FIFO exceeds the programmable
// empty threshold value.
.prog_full_axis(prog_full_axis), // 1-bit output: Programmable Full: This signal is asserted when
// the number of words in the FIFO is greater than or equal to
// the programmable full threshold value. It is de-asserted when
// the number of words in the FIFO is less than the programmable
// full threshold value.
.rd_data_count_axis(rd_data_count_axis), // RD_DATA_COUNT_WIDTH-bit output: Read Data Count- This bus
// indicates the number of words available for reading in the
// FIFO.
.s_axis_tready(s_axis_tready), // 1-bit output: TREADY: Indicates that the slave can accept a
// transfer in the current cycle.
.sbiterr_axis(sbiterr_axis), // 1-bit output: Single Bit Error- Indicates that the ECC
// decoder detected and fixed a single-bit error.
.wr_data_count_axis(wr_data_count_axis), // WR_DATA_COUNT_WIDTH-bit output: Write Data Count: This bus
// indicates the number of words written into the FIFO.
.injectdbiterr_axis(injectdbiterr_axis), // 1-bit input: Double Bit Error Injection- Injects a double bit
// error if the ECC feature is used.
.injectsbiterr_axis(injectsbiterr_axis), // 1-bit input: Single Bit Error Injection- Injects a single bit
// error if the ECC feature is used.
.m_aclk(m_aclk), // 1-bit input: Master Interface Clock: All signals on master
// interface are sampled on the rising edge of this clock.
.m_axis_tready(m_axis_tready), // 1-bit input: TREADY: Indicates that the slave can accept a
// transfer in the current cycle.
.s_aclk(s_aclk), // 1-bit input: Slave Interface Clock: All signals on slave
// interface are sampled on the rising edge of this clock.
.s_aresetn(s_aresetn), // 1-bit input: Active low asynchronous reset.
.s_axis_tdata(s_axis_tdata), // TDATA_WIDTH-bit input: TDATA: The primary payload that is
// used to provide the data that is passing across the
// interface. The width of the data payload is an integer number
// of bytes.
.s_axis_tdest(s_axis_tdest), // TDEST_WIDTH-bit input: TDEST: Provides routing information
// for the data stream.
.s_axis_tid(s_axis_tid), // TID_WIDTH-bit input: TID: The data stream identifier that
// indicates different streams of data.
.s_axis_tkeep(s_axis_tkeep), // TDATA_WIDTH/8-bit input: TKEEP: The byte qualifier that
// indicates whether the content of the associated byte of TDATA
// is processed as part of the data stream. Associated bytes
// that have the TKEEP byte qualifier deasserted are null bytes
// and can be removed from the data stream. For a 64-bit DATA,
// bit 0 corresponds to the least significant byte on DATA, and
// bit 7 corresponds to the most significant byte. For example:
// KEEP[0] = 1b, DATA[7:0] is not a NULL byte KEEP[7] = 0b,
// DATA[63:56] is a NULL byte
.s_axis_tlast(s_axis_tlast), // 1-bit input: TLAST: Indicates the boundary of a packet.
.s_axis_tstrb(s_axis_tstrb), // TDATA_WIDTH/8-bit input: TSTRB: The byte qualifier that
// indicates whether the content of the associated byte of TDATA
// is processed as a data byte or a position byte. For a 64-bit
// DATA, bit 0 corresponds to the least significant byte on
// DATA, and bit 0 corresponds to the least significant byte on
// DATA, and bit 7 corresponds to the most significant byte. For
// example: STROBE[0] = 1b, DATA[7:0] is valid STROBE[7] = 0b,
// DATA[63:56] is not valid
.s_axis_tuser(s_axis_tuser), // TUSER_WIDTH-bit input: TUSER: The user-defined sideband
// information that can be transmitted alongside the data
// stream.
.s_axis_tvalid(s_axis_tvalid) // 1-bit input: TVALID: Indicates that the master is driving a
// valid transfer. A transfer takes place when both TVALID and
// TREADY are asserted
);
// End of xpm_fifo_axis_inst instantiation