EFUSE_USR - 2021.2 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2021-10-22
Version
2021.2 English

Primitive: 32-bit non-volatile design ID

Introduction

Provides internal access to the 32 non-volatile, user-programmable eFUSE bits.

Port Descriptions

Port Direction Width Function
EFUSEUSR<31:0> Output 32 User eFUSE register value output.

Design Entry Method

Instantiation Recommended
Inference No
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
SIM_EFUSE _VALUE HEX 32'h00000000 to 32'hffffffff 32'h00000000 Value of the 32-bit non-volatile value used in simulation.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- EFUSE_USR: 32-bit non-volatile design ID
--            7 Series
-- Xilinx HDL Language Template, version 2021.2

EFUSE_USR_inst : EFUSE_USR
generic map (
   SIM_EFUSE_VALUE => X"00000000"  -- Value of the 32-bit non-volatile value used in simulation
)
port map (
   EFUSEUSR => EFUSEUSR  -- 32-bit output: User eFUSE register value output
);

-- End of EFUSE_USR_inst instantiation

Verilog Instantiation Template


// EFUSE_USR: 32-bit non-volatile design ID
//            7 Series
// Xilinx HDL Language Template, version 2021.2

EFUSE_USR #(
   .SIM_EFUSE_VALUE(32'h00000000)  // Value of the 32-bit non-volatile value used in simulation
)
EFUSE_USR_inst (
   .EFUSEUSR(EFUSEUSR)  // 32-bit output: User eFUSE register value output
);

// End of EFUSE_USR_inst instantiation

Related Information

  • See the 7 Series FPGAs Configuration Guide (UG470).