Primitive: Bi-Directional Differential Buffer with Input Termination Disable and Input Disable
Introduction
This design element is a bidirectional differential I/O buffer used to connect internal logic to an external bidirectional pin. This element includes an uncalibrated input termination (INTERM) disable as well as an input path disable as additional power saving features when the I/O is either is an unused state or being used as an output for a sustained amount of time. This element may only be placed in High Range (HR) banks in 7 series devices.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
IO | In/out | 1 | Bi-directional p-side port connection. Connect directly to top-level port in the design. |
IOB | In/out | 1 | Bi-directional n-side port connection. Connect directly to top-level port in the design. |
I | Input | 1 | Buffer input representing the output path to the device. |
IBUFDISABLE | Input | 1 | Disables input path through the buffer and forces to a logic high when USE_IBUFDISABLE is set to "TRUE". If USE_IBUFDISABLE is set to "FALSE" this input is ignored and should be tied to ground. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions. |
INTERMDISABLE | Input | 1 | Disables input termination. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions. |
T | Input | 1 | Sets the I/O in a high impedance 3-state mode when the I/O is being used for a read (input) operation. The T pin also affects the IBUFDISABLE function when USE_IBUFDISABLE = "TRUE". The T pin also disables INTERM when in a write (output) mode. |
O | Output | 1 | Buffer output representing the input path to the device. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP Catalog | Yes |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DIFF_TERM | STRING | "TRUE", "FALSE" | "FALSE" | Turns the built-in differential termination on (TRUE) or off (FALSE). |
IBUF_LOW_PWR | STRING | "TRUE", "FALSE" | "TRUE" | Allows a trade off of lower power consumption vs. highest performance when referenced I/O standards are used. |
IOSTANDARD | STRING | See Data Sheet | "DEFAULT" | Assigns an I/O standard to the element. |
SLEW | STRING | "SLOW" or "FAST" | "SLOW" | Sets the output rise and fall time. See the Data Sheet for recommendations of the best setting for this attribute. |
USE_IBUFDISABLE | STRING | "TRUE", "FALSE" | "TRUE" | Enables or disables the feature of IBUFDISABLE. Generally used when it is not desirable to have the T pin disable input path to allow a read during write operation. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IOBUFDS_INTERMDISABLE: Differential Bi-directional Buffer with Input Termination
-- and Input path enable/disable
-- May only be placed in High Range (HR) Banks
-- 7 Series
-- Xilinx HDL Language Template, version 2021.2
IOBUFDS_INTERMDISABLE_inst : IOBUFDS_INTERMDISABLE
generic map (
DIFF_TERM => "FALSE", -- Differential termination (TRUE/FALSE)
IBUF_LOW_PWR => "TRUE", -- Low Power - TRUE, HIGH Performance = FALSE
IOSTANDARD => "BLVDS_25", -- Specify the I/O standard
SLEW => "SLOW", -- Specify the output slew rate
USE_IBUFDISABLE => "TRUE") -- Use IBUFDISABLE function "TRUE" or "FALSE"
port map (
O => O, -- Buffer output
IO => IO, -- Diff_p inout (connect directly to top-level port)
IOB => IOB, -- Diff_n inout (connect directly to top-level port)
DCITERMDISABLE => DCITERMDISABLE, -- DCI Termination enable input
I => I, -- Buffer input
IBUFDISABLE => IBUFDISABLE, -- Input disable input, high=disable
INTERMDISABLE => INTERMDISABLE, -- Input termination disable input
T => T -- 3-state enable input, high=input, low=output
);
-- End of IOBUFDS_INTERMDISABLE_inst instantiation
Verilog Instantiation Template
// IOBUFDS_INTERMDISABLE: Differential Bi-directional Buffer with Input Termination
// and Input path enable/disable
// May only be placed in High Range (HR) Banks
// 7 Series
// Xilinx HDL Language Template, version 2021.2
IOBUFDS_INTERMDISABLE #(
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("BLVDS_25"), // Specify the I/O standard
.SLEW("SLOW"), // Specify the output slew rate
.USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
) IOBUFDS_INTERMDISABLE_inst (
.O(O), // Buffer output
.IO(IO), // Diff_p inout (connect directly to top-level port)
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
.I(I), // Buffer input
.IBUFDISABLE(IBUFDISABLE), // Input disable input, high=disable
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
.T(T) // 3-state enable input, high=input, low=output
);
// End of IOBUFDS_INTERMDISABLE_inst instantiation
Related Information
- See the 7 Series FPGA SelectIO Resources User Guide (UG471).