Primitive: Configuration Data Access
Introduction
The USR_ACCESSE2 design element enables access to the 32-bit AXSS register within the configuration logic. This enables FPGA logic to access static data that can be set from the bitstream. The USR_ACCESSE2 register AXSS can be used to provide a single 32-bit constant value to the FPGA logic. The register contents can be defined during bitstream generation, avoiding the need to re-compile the design as would be required if distributed RAM was used to hold the constant. A constant can be used to track the version of the design, or any other information you require.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| CFGCLK | Output | 1 | Configuration Clock output. |
| DATA<31:0> | Output | 32 | Configuration Data reflecting the contents of the AXSS register. |
| DATAVALID | Output | 1 | Active-High data valid output. |
Design Entry Method
| Instantiation | Recommended |
| Inference | No |
| IP Catalog | No |
| Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- USR_ACCESSE2: Configuration Data Access
-- 7 Series
-- Xilinx HDL Language Template, version 2021.2
USR_ACCESSE2_inst : USR_ACCESSE2
port map (
CFGCLK => CFGCLK, -- 1-bit output: Configuration Clock output
DATA => DATA, -- 32-bit output: Configuration Data output
DATAVALID => DATAVALID -- 1-bit output: Active high data valid output
);
-- End of USR_ACCESSE2_inst instantiation
Verilog Instantiation Template
// USR_ACCESSE2: Configuration Data Access
// 7 Series
// Xilinx HDL Language Template, version 2021.2
USR_ACCESSE2 USR_ACCESSE2_inst (
.CFGCLK(CFGCLK), // 1-bit output: Configuration Clock output
.DATA(DATA), // 32-bit output: Configuration Data output
.DATAVALID(DATAVALID) // 1-bit output: Active high data valid output
);
// End of USR_ACCESSE2_inst instantiation
Related Information
- See the 7 Series FPGAs Configuration Guide (UG470).