Primitive: 6-Input Look-Up Table with General Output
Introduction
This design element is a 6-input, 1-output look-up table (LUT) that can either act as an asynchronous 64-bit ROM (with 6-bit addressing) or implement any 6-input logic function. LUTs are the basic logic building blocks and are used to implement most logic functions of the design. A LUT6 is mapped to one of the four look-up tables in the slice. The functionality of the LUT6, LUT6_L and LUT6_D is the same. However, the LUT6_L and LUT6_D allow the additional specification to connect the LUT6 output signal to an internal slice, or CLB connection, using the LO output. The LUT6_L specifies that the only connections from the LUT6 will be within a slice, or CLB, while the LUT6_D allows the specification to connect the output of the LUT to both inter-slice/CLB logic and external logic as well. The LUT6 does not state any specific output connections and should be used in all cases except where internal slice or CLB signal connections must be implicitly specified.
An INIT attribute consisting of a 64-bit Hexadecimal value must be specified to indicate the LUTs logical function. The INIT value is calculated by assigning a 1 to corresponding INIT bit value when the associated inputs are applied. For instance, a Verilog INIT value of 64'h8000000000000000 (X"8000000000000000" for VHDL) makes the output zero unless all of the inputs are one (a 6-input AND gate). A Verilog INIT value of 64'hfffffffffffffffe (X"FFFFFFFFFFFFFFFE" for VHDL) makes the output one unless all zeros are on the inputs (a 6-input OR gate).
The INIT parameter for the FPGA LUT primitive gives the LUT its logical value. By default, this value is zero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in most cases a new INIT value must be determined to specify the logic function for the LUT primitive. There are at least two methods by which the LUT value can be determined.
- The Logic Table Method Create a binary logic table of all possible inputs, specify the desired logic value of the output and then create the INIT string from those output values.
- The Equation Method Define parameters for each input to the LUT that correspond to their listed truth value and use those to build the logic equation you are after. This method is easier to understand once you have grasped the concept and is more self-documenting than the above method. However, this method does require the code to first specify the appropriate parameters.
Logic Table
| Inputs | Outputs | |||||
|---|---|---|---|---|---|---|
| I5 | I4 | I3 | I2 | I1 | I0 | O |
| 0 | 0 | 0 | 0 | 0 | 0 | INIT[0] |
| 0 | 0 | 0 | 0 | 0 | 1 | INIT[1] |
| 0 | 0 | 0 | 0 | 1 | 0 | INIT[2] |
| 0 | 0 | 0 | 0 | 1 | 1 | INIT[3] |
| 0 | 0 | 0 | 1 | 0 | 0 | INIT[4] |
| 0 | 0 | 0 | 1 | 0 | 1 | INIT[5] |
| 0 | 0 | 0 | 1 | 1 | 0 | INIT[6] |
| 0 | 0 | 0 | 1 | 1 | 1 | INIT[7] |
| 0 | 0 | 1 | 0 | 0 | 0 | INIT[8] |
| 0 | 0 | 1 | 0 | 0 | 1 | INIT[9] |
| 0 | 0 | 1 | 0 | 1 | 0 | INIT[10] |
| 0 | 0 | 1 | 0 | 1 | 1 | INIT[11] |
| 0 | 0 | 1 | 1 | 0 | 0 | INIT[12] |
| 0 | 0 | 1 | 1 | 0 | 1 | INIT[13] |
| 0 | 0 | 1 | 1 | 1 | 0 | INIT[14] |
| 0 | 0 | 1 | 1 | 1 | 1 | INIT[15] |
| 0 | 1 | 0 | 0 | 0 | 0 | INIT[16] |
| 0 | 1 | 0 | 0 | 0 | 1 | INIT[17] |
| 0 | 1 | 0 | 0 | 1 | 0 | INIT[18] |
| 0 | 1 | 0 | 0 | 1 | 1 | INIT[19] |
| 0 | 1 | 0 | 1 | 0 | 0 | INIT[20] |
| 0 | 1 | 0 | 1 | 0 | 1 | INIT[21] |
| 0 | 1 | 0 | 1 | 1 | 0 | INIT[22] |
| 0 | 1 | 0 | 1 | 1 | 1 | INIT[23] |
| 0 | 1 | 1 | 0 | 0 | 0 | INIT[24] |
| 0 | 1 | 1 | 0 | 0 | 1 | INIT[25] |
| 0 | 1 | 1 | 0 | 1 | 0 | INIT[26] |
| 0 | 1 | 1 | 0 | 1 | 1 | INIT[27] |
| 0 | 1 | 1 | 1 | 0 | 0 | INIT[28] |
| 0 | 1 | 1 | 1 | 0 | 1 | INIT[29] |
| 0 | 1 | 1 | 1 | 1 | 0 | INIT[30] |
| 0 | 1 | 1 | 1 | 1 | 1 | INIT[31] |
| 1 | 0 | 0 | 0 | 0 | 0 | INIT[32] |
| 1 | 0 | 0 | 0 | 0 | 1 | INIT[33] |
| 1 | 0 | 0 | 0 | 1 | 0 | INIT[34] |
| 1 | 0 | 0 | 0 | 1 | 1 | INIT[35] |
| 1 | 0 | 0 | 1 | 0 | 0 | INIT[36] |
| 1 | 0 | 0 | 1 | 0 | 1 | INIT[37] |
| 1 | 0 | 0 | 1 | 1 | 0 | INIT[38] |
| 1 | 0 | 0 | 1 | 1 | 1 | INIT[39] |
| 1 | 0 | 1 | 0 | 0 | 0 | INIT[40] |
| 1 | 0 | 1 | 0 | 0 | 1 | INIT[41] |
| 1 | 0 | 1 | 0 | 1 | 0 | INIT[42] |
| 1 | 0 | 1 | 0 | 1 | 1 | INIT[43] |
| 1 | 0 | 1 | 1 | 0 | 0 | INIT[44] |
| 1 | 0 | 1 | 1 | 0 | 1 | INIT[45] |
| 1 | 0 | 1 | 1 | 1 | 0 | INIT[46] |
| 1 | 0 | 1 | 1 | 1 | 1 | INIT[47] |
| 1 | 1 | 0 | 0 | 0 | 0 | INIT[48] |
| 1 | 1 | 0 | 0 | 0 | 1 | INIT[49] |
| 1 | 1 | 0 | 0 | 1 | 0 | INIT[50] |
| 1 | 1 | 0 | 0 | 1 | 1 | INIT[51] |
| 1 | 1 | 0 | 1 | 0 | 0 | INIT[52] |
| 1 | 1 | 0 | 1 | 0 | 1 | INIT[53] |
| 1 | 1 | 0 | 1 | 1 | 0 | INIT[54] |
| 1 | 1 | 0 | 1 | 1 | 1 | INIT[55] |
| 1 | 1 | 1 | 0 | 0 | 0 | INIT[56] |
| 1 | 1 | 1 | 0 | 0 | 1 | INIT[57] |
| 1 | 1 | 1 | 0 | 1 | 0 | INIT[58] |
| 1 | 1 | 1 | 0 | 1 | 1 | INIT[59] |
| 1 | 1 | 1 | 1 | 0 | 0 | INIT[60] |
| 1 | 1 | 1 | 1 | 0 | 1 | INIT[61] |
| 1 | 1 | 1 | 1 | 1 | 0 | INIT[62] |
| 1 | 1 | 1 | 1 | 1 | 1 | INIT[63] |
| INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute | ||||||
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| O | Output | 1 | 6/5-LUT output |
| I0, I1, I2, I3, I4, I5 | Input | 1 | LUT inputs |
Design Entry Method
| Instantiation | Yes |
| Inference | Recommended |
| IP Catalog | No |
| Macro support | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| INIT | HEX | Any 64-Bit Value | All zeros | Initializes look-up tables. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT6: 6-input Look-Up Table with general output
-- 7 Series
-- Xilinx HDL Language Template, version 2021.2
LUT6_inst : LUT6
generic map (
INIT => X"0000000000000000") -- Specify LUT Contents
port map (
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3, -- LUT input
I4 => I4, -- LUT input
I5 => I5 -- LUT input
);
-- End of LUT6_inst instantiation
Verilog Instantiation Template
// LUT6: 6-input Look-Up Table with general output
// 7 Series
// Xilinx HDL Language Template, version 2021.2
LUT6 #(
.INIT(64'h0000000000000000) // Specify LUT Contents
) LUT6_inst (
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2), // LUT input
.I3(I3), // LUT input
.I4(I4), // LUT input
.I5(I5) // LUT input
);
// End of LUT6_inst instantiation
Related Information
- See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).