Primitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs
Introduction
This design element allows for an input, 3-state output, or bi-directional port to be driven to a weak high value when not being driven by an internal or external source. This element establishes a High logic level for open-drain elements and macros when all the drivers are off.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| O | Output | 1 | Pullup output (connect directly to top level port) |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP Catalog | No |
| Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- PULLUP: I/O Buffer Weak Pull-up
-- 7 Series
-- Xilinx HDL Language Template, version 2021.2
PULLUP_inst : PULLUP
port map (
O => O -- Pullup output (connect directly to top-level port)
);
-- End of PULLUP_inst instantiation
Verilog Instantiation Template
// PULLUP: I/O Buffer Weak Pull-up
// 7 Series
// Xilinx HDL Language Template, version 2021.2
PULLUP PULLUP_inst (
.O(O) // Pullup output (connect directly to top-level port)
);
// End of PULLUP_inst instantiation
Related Information
- See the 7 Series FPGA SelectIO Resources User Guide (UG471).