Macro: Multiplier/Accumulator
Introduction
MACC_MACRO simplifies the instantiation of the DSP48 block when used in simple signed multiplier/accumulator mode. It features parameterizable input and output widths and latencies that ease the integration of the DSP48 block into HDL.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
P | Output | Variable width, equals the value of the WIDTH_A attribute plus the value of the WIDTH_B attribute. | Primary data output. |
A | Input | Variable, see WIDTH_A attribute. | Multiplier data input. |
B | Input | Variable, see WIDTH_B attribute. | Multiplier data input. |
CARRYIN | Input | 1 | Carry input. |
CE | Input | 1 | Clock enable. |
CLK | Input | 1 | Clock. |
LOAD | Input | 1 | Load. |
LOAD_DATA | Input | Variable width, equals the value of the WIDTH_A attribute plus the value of the WIDTH_B attribute. | In a DSP slice, when LOAD is asserted, loads P with A*B+LOAD_DATA. |
RST | Input | 1 | Synchronous Reset. |
ADDSUB | Input | 1 | High sets accumulator in addition mode; low sets accumulator in subtraction mode. |
Design Entry Method
This unimacro is a parameterizable version of the primitive, and can be
instantiated only.
Instantiation | Yes |
Inference | No |
IP Catalog | No |
Macro support | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DEVICE | STRING | "7SERIES" | "7SERIES" | Target hardware architecture. |
WIDTH_P | INTEGER | 1 to 48 | 48 | Accumulator output bus width. |
WIDTH_A | INTEGER | 1 to 25 | 25 | Multiplier A-input bus width. |
WIDTH_B | INTEGER | 1 to 18 | 18 | Multiplier B-input bus width. |
LATENCY | INTEGER | 1, 2, 3, 4 | 3 | Number of pipeline registers.
|
VHDL Instantiation Template
Unless
they already exist, copy the following four statements and paste them
before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
-- MACC_MACRO: Multiple Accumulate Function implemented in a DSP48E
-- 7 Series
-- Xilinx HDL Language Template, version 2021.2
MACC_MACRO_inst : MACC_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
LATENCY => 3, -- Desired clock cycle latency, 1-4
WIDTH_A => 25, -- Multiplier A-input bus width, 1-25
WIDTH_B => 18, -- Multiplier B-input bus width, 1-18
WIDTH_P => 48) -- Accumulator output bus width, 1-48
port map (
P => P, -- MACC ouput bus, width determined by WIDTH_P generic
A => A, -- MACC input A bus, width determined by WIDTH_A generic
ADDSUB => ADDSUB, -- 1-bit add/sub input, high selects add, low selects subtract
B => B, -- MACC input B bus, width determined by WIDTH_B generic
CARRYIN => CARRYIN, -- 1-bit carry-in input to accumulator
CE => CE, -- 1-bit active high input clock enable
CLK => CLK, -- 1-bit positive edge clock input
LOAD => LOAD, -- 1-bit active high input load accumulator enable
LOAD_DATA => LOAD_DATA, -- Load accumulator input data,
-- width determined by WIDTH_P generic
RST => RST -- 1-bit input active high reset
);
-- End of MACC_MACRO_inst instantiation
Verilog Instantiation Template
// MACC_MACRO: Multiply Accumulate Function implemented in a DSP48E
// 7 Series
// Xilinx HDL Language Template, version 2021.2
MACC_MACRO #(
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.LATENCY(3), // Desired clock cycle latency, 1-4
.WIDTH_A(25), // Multiplier A-input bus width, 1-25
.WIDTH_B(18), // Multiplier B-input bus width, 1-18
.WIDTH_P(48) // Accumulator output bus width, 1-48
) MACC_MACRO_inst (
.P(P), // MACC output bus, width determined by WIDTH_P parameter
.A(A), // MACC input A bus, width determined by WIDTH_A parameter
.ADDSUB(ADDSUB), // 1-bit add/sub input, high selects add, low selects subtract
.B(B), // MACC input B bus, width determined by WIDTH_B parameter
.CARRYIN(CARRYIN), // 1-bit carry-in input to accumulator
.CE(CE), // 1-bit active high input clock enable
.CLK(CLK), // 1-bit positive edge clock input
.LOAD(LOAD), // 1-bit active high input load accumulator enable
.LOAD_DATA(LOAD_DATA), // Load accumulator input data, width determined by WIDTH_P parameter
.RST(RST) // 1-bit input active high reset
);
// End of MACC_MACRO_inst instantiation