IOBUFDS - 2021.2 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2021-10-22
Version
2021.2 English

Primitive: 3-State Differential Signaling I/O Buffer with active-Low Output Enable

Introduction

The design element is a bidirectional buffer that supports low-voltage, differential signaling. For the IOBUFDS, a design level interface signal is represented as two distinct ports (IO and IOB), one deemed the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available to help improve signal integrity and reduce external components. Also available is a programmable delay is to assist in the capturing of incoming data to the device.

Logic Table

Inputs Bidirectional Outputs
I T IO IOB O
X 1 Z Z No Change
0 0 0 1 0
I 0 1 0 1

Port Descriptions

Port Direction Width Function
O Output 1 Buffer output.
IO In/out 1 Diff_p In/out.
IOB In/out 1 Diff_n In/out.
I Input 1 Buffer input.
T Input 1 3-state enable input.

Design Entry Method

Instantiation Recommended
Inference No
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
DIFF_TERM BOOLEAN TRUE, FALSE FALSE Turns the built-in differential termination on (TRUE) or off (FALSE).
IBUF_LOW_PWR BOOLEAN TRUE, FALSE TRUE When set to TRUE, allows for reduced power when using differential or referenced (requiring VREF) input standards like LVDS or HSTL. A setting of FALSE demands more power but delivers higher performance characteristics. Consult the7 Series FPGA SelectIO Resources User Guide (UG471) for details.
IOSTANDARD STRING See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
SLEW STRING "SLOW" or "FAST" "SLOW" Specifies the slew rate of the output driver. Consult the product Data Sheet for recommendations of the best setting for this attribute.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IOBUFDS: Differential Bi-directional Buffer
--          7 Series
-- Xilinx HDL Language Template, version 2021.2

IOBUFDS_inst : IOBUFDS
generic map (
   DIFF_TERM => FALSE, -- Differential Termination (TRUE/FALSE)
   IBUF_LOW_PWR => TRUE, -- Low Power = TRUE, High Performance = FALSE
   IOSTANDARD => "BLVDS_25", -- Specify the I/O standard
   SLEW => "SLOW")       -- Specify the output slew rate
port map (
   O => O,     -- Buffer output
   IO => IO,   -- Diff_p inout (connect directly to top-level port)
   IOB => IOB, -- Diff_n inout (connect directly to top-level port)
   I => I,     -- Buffer input
   T => T      -- 3-state enable input, high=input, low=output
);

-- End of IOBUFDS_inst instantiation

Verilog Instantiation Template


// IOBUFDS: Differential Bi-directional Buffer
//          7 Series
// Xilinx HDL Language Template, version 2021.2

IOBUFDS #(
   .DIFF_TERM("FALSE"),     // Differential Termination ("TRUE"/"FALSE")
   .IBUF_LOW_PWR("TRUE"),   // Low Power - "TRUE", High Performance = "FALSE"
   .IOSTANDARD("BLVDS_25"), // Specify the I/O standard
   .SLEW("SLOW")            // Specify the output slew rate
) IOBUFDS_inst (
   .O(O),     // Buffer output
   .IO(IO),   // Diff_p inout (connect directly to top-level port)
   .IOB(IOB), // Diff_n inout (connect directly to top-level port)
   .I(I),     // Buffer input
   .T(T)      // 3-state enable input, high=input, low=output
);

// End of IOBUFDS_inst instantiation

Related Information

  • See the 7 Series FPGA SelectIO Resources User Guide (UG471).