When the build target is the hardware, v++
builds the FPGA binary for the Xilinx device by
running Vivado synthesis and implementation on the
design. It is normal for this build target to take a longer period of time than
generating either the software or hardware emulation targets in the Vitis IDE. However, the final FPGA binary can be loaded
into the hardware of the accelerator card, or embedded processor platform, and the
application can be run in its actual operating environment.
As discussed in Vitis Compiler Command, the
system hardware target is specified in the v++ command
with the -t option:
v++ -t hw ...