Divide Logic Functions to Platform and Kernel
While the designs on FPGA and SoC are getting more complex, it is common for multiple developers or teams to work on a design together. The Vitis software platform provides a clear boundary for application developers and platform developers. Platform developers might include board developers, BSP developers, system software developers, and so on.
In the view of a system architect, some logic functions might be in a gray area: they can be packaged grouped with platforms, or they can work as an acceleration kernel. To help divide the system blocks, here are some general guidelines.
- The basic consideration for classifying a function as a kernel or platform is whether it is an application-related logic.
- Platforms should be more stable than applications. Application function changes should only happen in the software and kernel.
- Platforms abstract hardware. When changing a hardware board, the application should need no change, or very little change if necessary, to target to the new hardware.
- Follow constraints and limitations of the Vitis tool. For
example:
- Only three types of interfaces are supported by Vitis acceleration kernels: AXI MM, AXI4-Lite, and AXI4-Stream.
- AXI Kernel does not support external I/O pins.
The following table shows the recommended platforms and kernels for logic types.
| Logic | Platform | Kernel |
|---|---|---|
| Hard Processors (PS of Zynq and Zynq UltraScale+ MPSoC) | Only in Platform | |
| Soft Processors | Preferred in Platform | OK as an RTL kernel |
| I/O Block (External pins, MIPI, PHY, etc.) | Only in Platform | |
| Related IP for I/O Block (DMA for PCIe® , MAC for Ethernet, etc.) | Generally in platform because the interface between I/O and IP are not AXI. | OK as Kernel if the interfaces between I/O block and IP are AXI. |
| IP with non-AXI interface | Only in Platform | OK if the interface can be changed to AXI MM or AXI4-Stream |
| Traditional memory mapped IP which has Linux driver (VPSS, etc.) | Only in Platform | |
| HLS AXI memory mapped IP | OK in Platform. You have to write control software. | Preferred as Kernel. Controlled by XRT. |
| Acceleration memory mapped IP follows Vitis kernel register standard and open to XRT | Preferred as Kernel | |
| Vitis Libraries | Only work as Kernel | |
| Free running IP with AXI4-Stream interface | OK | OK |
References
For more information on embedded platforms, see the following links: