RTL Kernels

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
Release Date
2020.2 English

In the Vitis application acceleration development flow, C++ source code can be compiled into Xilinx® object (XO) files that can be linked with a target platform into an FPGA executable (XCLBIN). RTL IP from the Vivado® Design Suite can also be packaged as XO files that can be linked into an XCLBIN, as long as they adhere to Vivado IP Packaging guidelines, and requirements of the Vitis compiler. Those requirements are described here.