Capturing the data required for the Profile Summary requires a few steps prior to actually running the application.
- The FPGA binary (xclbin) file is
configured for capturing profiling data by default. However, using the
v++ --profile
option during the linking process enables a greater level of detail in the profiling data captured. For more information, see the --profile Options. - The runtime requires the presence of an xrt.ini file, as described in xrt.ini File, that includes the keyword for capturing profiling data:
[Debug] profile = true
- To enable the profiling of Kernel Internals data, you must also add the
debug_mode
tag in the[Emulation]
section of the xrt.ini:[Emulation] debug_mode = batch
With profiling enabled in the device binary and in the xrt.ini file, the runtime creates the profile_summary.csv report file when running the application, and also creates the profile_kernels.csv and timeline_kernels.csv files when Kernel Internals is enabled. These files are linked to the Profile Summary report which can be viewed in the Vitis analyzer tool through the Run Summary. Open the Run Summary using the following command:
vitis_analyzer <project>.run_summary