Clock and Reset Requirements - 2020.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID
UG1393
Release Date
2021-03-22
Version
2020.2 English
Table 1. Requirements
C/C++/OpenCL C Kernel RTL Kernel
C kernel does not require any input from user on clock ports and reset ports. The HLS tool will always generate RTL with clock port ap_clk and reset port ap_rst_n.
  • Requires a clock port. Must be named ap_clk.
  • Optional clock port. Must be named ap_clk_2.
  • Optional reset port. Must be named ap_rst_n. This signal is driven by the synchronous reset in the ap_clk clock domain.
  • This reset signal is active-Low.
  • Another optional reset port. Must be named ap_rst_n_2. This signal is driven by synchronous reset in the ap_clk_2 clock domain.