The following example shows the directory structure automatically generated by the Vitis IDE for a sample application acceleration project which includes:
- Top-level system project
- Host application project
- Hardware kernel compilation project
- Hardware kernel linking project
The default directory structure of the Vitis IDE is similar but not identical to that created by the command-line flow.
### Vitis IDE Directory Structure
workspace
>pathwayKernel - a hardware kernel project in the Vitis application acceleration development flow. The top-level project can contain multiple kernel projects.
>Emulation-HW - the hardware emulation build folder.
>build
> The build folder for the compiled hardware kernel (.XO)
>guidance.html
>guidance.json
>guidance.pb
>makefile
>mmult-compile.cfg
>pathwayKernel_Emulation-HW.build.ui.log
>xcd.log
>Emulation-SW
>Files related to the Software Emulation Build
>pathwayKernel.prj - Hardware kernel project
>src - Hardware kernel source files
>kernel.cpp
>pathwayTest - The host application project
>Emulation-HW
>au250_image.jpg
>bd_d216_ddr4_mem00_0_microblaze_mcs_bd.tcl
>bd_d216_ddr4_mem00_0_microblaze_mcs.hwh
>bd_d216_ddr4_mem01_0_microblaze_mcs_bd.tcl
>bd_d216_ddr4_mem01_0_microblaze_mcs.hwh
>bd_d216_ddr4_mem02_0_microblaze_mcs_bd.tcl
>bd_d216_ddr4_mem02_0_microblaze_mcs.hwh
>bd_d216_ddr4_mem03_0_microblaze_mcs_bd.tcl
>bd_d216_ddr4_mem03_0_microblaze_mcs.hwh
>bd_d216_interconnect_DDR4_MEM00_0_bd.tcl
>bd_d216_interconnect_DDR4_MEM00_0.hwh
>bd_d216_interconnect_DDR4_MEM01_0_bd.tcl
>bd_d216_interconnect_DDR4_MEM01_0.hwh
>bd_d216_interconnect_DDR4_MEM02_0_bd.tcl
>bd_d216_interconnect_DDR4_MEM02_0.hwh
>bd_d216_interconnect_DDR4_MEM03_0_bd.tcl
>bd_d216_interconnect_DDR4_MEM03_0.hwh
>bd_d216_interconnect_PLRAM_MEM00_0_bd.tcl
>bd_d216_interconnect_PLRAM_MEM00_0.hwh
>bd_d216_interconnect_PLRAM_MEM01_0_bd.tcl
>bd_d216_interconnect_PLRAM_MEM01_0.hwh
>bd_d216_interconnect_PLRAM_MEM02_0_bd.tcl
>bd_d216_interconnect_PLRAM_MEM02_0.hwh
>bd_d216_interconnect_PLRAM_MEM03_0_bd.tcl
>bd_d216_interconnect_PLRAM_MEM03_0.hwh
>bd_d216_interconnect_S00_AXI_0_bd.tcl
>bd_d216_interconnect_S00_AXI_0.hwh
>bd_d216_interconnect_S01_AXI_0_bd.tcl
>bd_d216_interconnect_S01_AXI_0.hwh
>bd_d216_interconnect_S02_AXI_0_bd.tcl
>bd_d216_interconnect_S02_AXI_0.hwh
>bd_d216_interconnect_S03_AXI_0_bd.tcl
>bd_d216_interconnect_S03_AXI_0.hwh
>binary_container_1.xclbin
>board
>board files for the selected hardware platform
>dsa.xml
>emconfig.json
>emu
>dynamic_post_sys_link.tcl
>dynamic_pre_sys_link.tcl
>emu.bd
>emu.bxml
>emu.xml
>hdl
>emu_wrapper.v
>ip
>IP files from the selected platform
>ipshared
>
>prop.json
>sim
>
>synth
>
>emulation_debug.log
>ext_metadata.json
>firmware
>xilinx_u250_xdma_201830_3.mcs
>xilinx_u250_xdma_201830_3.prm
>guidance.html
>guidance.json
>guidance.pb
>launch_options.cfg
>makeemconfig.mk
>makefile
>pathwayTest
>pathwayTest_Emulation-HW.build.ui.log
>pfm_dynamic_bd.tcl
>pfm_dynamic_debug_bridge_xsdbm_0_bd.tcl
>pfm_dynamic_debug_bridge_xsdbm_0.hwh
>pfm_dynamic.hwh
>pfm_dynamic_memory_subsystem_0_bd.tcl
>pfm_dynamic_memory_subsystem_0.hwh
>pfm_top_bd.tcl
>pfm_top.hwh
>pfm_top_jtag_fallback_0_bd.tcl
>pfm_top_jtag_fallback_0.hwh
>pfm_top_mgmt_debug_bridge_0_bd.tcl
>pfm_top_mgmt_debug_bridge_0.hwh
>pfm_top_mgmt_debug_hub_0_bd.tcl
>pfm_top_mgmt_debug_hub_0.hwh
>pfm_top_user_debug_bridge_0_bd.tcl
>pfm_top_user_debug_bridge_0.hwh
>pfm_top_user_debug_hub_0_bd.tcl
>pfm_top_user_debug_hub_0.hwh
>src
>host.cpp
>sysdef.xml
>SystemDebugger_pathwayTest_system_pathwayTest
>binary_container_1.xclbin.run_summary
>guidance.html
>guidance.json
>guidance.pb
>profile_guidance.json
>profile_guidance.pb
>profile_kernels.csv
>profile_summary.csv
>profile_summary.xprf
>timeline_kernels.csv
>timeline_trace.csv
>xilinx_u250_xdma_201830_3-0-binary_container_1.protoinst
>xilinx_u250_xdma_201830_3-0-binary_container_1_simulate.log
>xilinx_u250_xdma_201830_3-0-binary_container_1.wcfg
>xilinx_u250_xdma_201830_3-0-binary_container_1.wdb
>xilinx_u250_xdma_201830_3-0-binary_container_1_xsc_report.log
>xrc.log
>xrt.ini
>SystemDebugger_pathwayTest_system_pathwayTest.launch.log
>SystemDebugger_pathwayTest_system_pathwayTest.launch.ui.log
>tcl_hooks
>dynamic_postlink.tcl
>dynamic_postopt.tcl
>dynamic_prelink.tcl
>xilinx_u250_xdma_201830_3_dynamic_impl.xdc
>update_dsa.log
>xilinx_u250_xdma_201830_3.hpfm
>Emulation-SW
>pathwayTest.prj
>src
>kernel.cpp
>pathwayTest_system
>binary_container_1.xclbin
>binary_container_1.xclbin.package_summary
>makefile
>package.build
>logs
>package
>system diagram and package project
>reports
>package
>v++_package_binary_container_1_guidance.html
>v++_package_binary_container_1_guidance.json
>v++_package_binary_container_1_guidance.pb
>package.cfg
>pathwayTest_system_Emulation-HW.build.ui.log
>v++_binary_container_1.log
>xcd.log
>xrc.log
>pathwaytTest_system_hw_link
>binary_container_1.build
>link
>activetask.json
>int
>address_map.xml
>appendSection.rtd
>behav_waveform
>xsim
>behav.xse
>binary_container_1_build.rtd
>binary_container_1.gpp_so.log
>binary_container_1.rtd
>binary_container_1.so
>binary_container_1.xml
>binary_container_1_xml.rtd
>cf2sw_full.rtd
>cf2sw.rtd
>consolidated.cf
>debug_ip_layout.rtd
>dr.bd.tcl
>kernel_info.dat
>_kernel_inst_paths.dat
>kernel_service.json
>mmult
>
>_new_clk_freq
>sdsl.dat
>syslinkConfig.ini
>systemDiagramModel.json
>systemDiagramModelSlrBaseAddress.json
>vplConfig.ini
>vplsettings.json
>xclbin_orig.1.xml
>xclbin_orig.xml
>xclbin_orig.xml.tmp
>xo
>ip_repo
>mmult
>cpu_sources
>debug
>kernel.xml
>mmult.design.xml
>link.spr
>link.steps.log
>run_link
>sys_link
>vivado
>logs
>link
>reports
>link
>binary_container_1-link.cfg
>binary_container_1.mdb
>binary_container_1.xclbin
>binary_container_1.xclbin.info
>binary_container_1.xclbin.link_summary
>binary_container_1.xclbin.sh
>guidance.html
>guidance.json
>guidance.pb
>makefile
>pathwayTest_system_hw_link_Emulation-HW.build.ui.log
>xcd.log