Kernel Interface Requirements

Kernel Interface Requirements - 2020.2 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)

Document ID

UG1393

Release Date

2021-03-22

Version

2020.2 English

To satisfy the Vitis core development kit execution model, an RTL kernel must adhere to the requirements described in Kernel Properties. The RTL kernel must have at least one clock interface port to supply a clock to the kernel logic. The various interface requirements are summarized in the following table.

Important: In some cases, the port names must be written exactly as shown.

Table 1. RTL Kernel Interface and Port Requirements
Port or Interface	Description	Comment
ap_clk	Primary clock input port	Required port. Name must be exact.
ap_clk_2	Secondary optional clock input port	Optional port. Name must be exact.
ap_rst_n	Primary active-Low reset input port	Optional port. Name must be exact. This signal should be internally pipelined to improve timing. This signal is driven by a synchronous reset in the ap_clk clock domain.
ap_rst_n_2	secondary optional active-Low reset input	Optional port. Name must be exact. This signal should be internally pipelined to improve timing. This signal is driven by a synchronous reset in the ap_clk_2 clock domain.
interrupt	Active-High interrupt.	Optional port. Name must be exact.
s_axi_control	One (and only one) AXI4-Lite slave control interface	Required port* Name must be exact; case sensitive. Note: * The port is generally required, though there are exceptions such as the Free-Running Kernel.
AXI4_MASTER	One or more AXI4 master interfaces for global memory access	Optional port. All AXI4 master interfaces must have 64-bit addresses (32 bits on Zynq-7000 devices). The RTL kernel developer is responsible for partitioning global memory spaces. Each partition in the global memory becomes a kernel argument. The memory offset for each partition must be set by a control register programmable via the AXI4-Lite slave interface. AXI4 masters must not use Wrap or Fixed burst types and must not use narrow (sub-size) bursts meaning AxSIZE should match the width of the AXI data bus. Any user logic or RTL code that does not conform to the requirements above, must be wrapped or bridged to satisfy these requirements.
AXI4_STREAM	One or more AXI4-Streaminterfaces for one-way data transfers between kernels or between the host application and kernels.	Optional port. Cannot be used with bi-directional ports. Use the STREAM interface template in the Vivado Design Suite. Refer to AXI4-Stream Interfaces in Vitis High-Level Synthesis User Guide (UG1399) for additional information on interface requirements.