In the Vivado Design Suite, the
following create_clock constraints differ.
-
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk] -
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_pins clk_IBUF_BUFG_inst/O]
The constraints differ because they use different start points to
define the time zero that the Vivado IDE assigns
when computing the clock latency and uncertainty for the slack equation. See the
figure below.
Figure 1. Clocking Structure Example from a Clock Pad through
BUFG
The Vivado IDE ignores all clock tree delays coming from cells located upstream from the point at which the primary clock is defined. If you define a primary clock on a pin in the middle of the design, only part of its latency is used for timing analysis. This can be an issue if this clock communicates with other related clocks in the design because the skew, and consequently the slack, value between the clocks can be inaccurate.
Use the create_clock command where
the clock trees originate not in the middle of the design (for example, input port
or GT clock output pin). Create generated clocks in the middle of the design
only.