The following ISE Design Suite timing constraints can be represented as XDC timing constraints in the Vivado Design Suite. Each constraint description contains a UCF example and the equivalent XDC example.
UCF and XDC differ when creating clocks on a net that is not directly connected
to the boundary of the design (such as port). In XDC, when defining a primary clock with
create_clock on a net the source point is the driving pin of the
net.
The clock insertion delay before that point is ignored. This can be an issue when timing the clock with another related clock; the skew will not be accurate.