Constraint Sequence - 2023.2 English

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2023-11-01
Version
2023.2 English

Whether you use one or more XDC files for your design, AMD recommends that you organize your constraints in the following sequence:

## Timing Assertions Section

# Primary clocks

# Virtual clocks

# Generated clocks

# Clock Groups

# Input and output delay constraints

## Timing Exceptions Section (sorted by precedence)

# False Paths

# Max Delay / Min Delay

# Multicycle Paths

# Case Analysis

# Disable Timing

## Physical Constraints Section

# located anywhere in the file, preferably before or after the timing constraints

# or stored in a separate XDC file