Clock and Resets - 2024.1 English

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2024-05-30
Version
2024.1 English

XPS provides a central clocking mechanism through use of the Clock Generator IP. The clock generator recognizes the clock requirements for all IP and generates the desired MMCM/PLL configurations as part of the IP.

In the IP integrator, use the clocking_wizard for clock configuration.

Important: You must enter the desired frequency as part of the clocking wizard IP. The properties of the generated clocks (such as frequency and phase) are propagated from the Clocking IP to the individual IP through use of the parameter propagation methods implemented by the IP.
See the following documents for more information:
  • Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898)
  • Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
  • Vivado Design Suite User Guide: Designing with IP (UG896)