Mapping ISE Design Suite Command Scripts - 2024.1 English

ISE to Vivado Design Suite Migration Guide (UG911)
Document ID
UG911
Release Date
2024-05-30
Version
2024.1 English

This section covers the Vivado Design Suite non-project design flow mode only, and is intended for those who plan to use Tcl scripting with the Vivado tools.

You can use Tcl scripts to migrate your ISE Design Suite scripts to implement your design. Similar to the ISE Design Suite, the compilation flow in the Vivado Design Suite translates the design, maps the translated design to device-specific elements, optimizes the design, places and routes the design, and then generates a BIT file for programming.

The following table shows the main differences between the two design flows.

Table 1. ISE Design Suite versus Vivado Design Suite Design Flow
ISE Design Suite Vivado Design Suite
Separate command line applications Tcl commands in a shell.
XCF/NCF/UCF/PCF constraints XDC timing and physical constraints
Design constraints (timing or physical) only applied at beginning of the flow Constraints (timing or physical) can be applied, changed, or removed at any point in the flow.
Multiple database files (NGC, NGD, NCD) required A single design database (checkpoint with a .dcp extension) written out on-demand at any point in the flow.
Reports generated by applications Reports generated on-demand at any point in the flow, where applicable.

The following table shows the mapping of Design Suite commands to corresponding Vivado Design Suite Tcl commands. You can run the Tcl commands using any of the following:

  • In the Vivado IDE Tcl Console
  • At the Tcl prompt (vivado -mode tcl)
  • Through a batch script (vivado -mode batch -source my.tcl)
Table 2. ISE Design Suite Commands and Vivado Design Suite Tcl Commands
ISE Design Suite Command Vivado Design Suite Tcl Command
xst

read_verilog

read_vhdl

read_xdc

synth_design
Note: The commands must be run in this order.
ngdbuild

read_edif

read_xdc

link_design

Note:
  • You need these commands if you are importing from third-party synthesis. If using synth_design, omit these steps.
  • If you are using the Non-Project flow, you need to use the read_edif command to include the NGC file.
map

opt_design

power_opt_design (optional)

place_design

phys_opt_design (optional)
par route_design
trce

report_timing

report_timing_summary

xpwr

read_saif

report_power

drc report_drc
netgen

write_verilog

write_vhdl

write_sdf

bitgen write_bitstream
xinfo report_environment

The ISE Design Suite and the Vivado Design Suite uses different algorithms; consequently, a one-to-one mapping is not always possible between the two tool flows. The following table provides a mapping of frequently-used options between the two implementation flows.

Table 3. ISE to Vivado Implementation Flow Mappings
ISE Design Suite Vivado Design Suite
ngdbuild -p partname link_design -part
ngdbuild -a (insert pads) synth_design -no_iobuf (opposite)
ngdbuild -u (unexpanded blocks) Allowed by default, generates critical warnings.
ngdbuild -quiet link_design -quiet
map -detail opt_design -verbose
map -lc auto Feature is no longer needed. Vivado automatically uses less area in quest for better routability and QOR.
map -logic_opt opt_design, phys_opt_design
map -mt place_design automatically runs MT with four cores in Linux or two cores in Windows.
map -ntd place_design -non_timing_driven
map -ol place_design -directive 1
map -power power_opt_design
map -u link_design -mode out_of_context, opt_design -retarget (skip constant propagation and sweep)
par -pl place_design -directive 1
par -rl route_design -directive 1
par -mt route_design automatically runs MT with four cores in Linux or two core in Windows
par -k (keep existing placement and routing) Default behavior for route_design
par -nopad report_io generates pad report
par -ntd route_design -no_timing_driven
  1. See the Tcl help for more information on the -directive option.