You can combine legacy ChipScope™ cores with Vivado core using the following rules:
- You can either instantiate Vivado debug IP cores in your
HDL code or you can insert the ILA v2.0 core into the netlist of the Vivado design.Note: The
dbg_hubcore that connects your Vivado debug IP cores to the JTAG infrastructure is automatically inserted into your design. - You must instantiate the legacy ChipScope Pro debug IP
cores into your HDL code. Note: Debug core insertion into the Vivado design netlist is not supported for legacy ChipScope Pro debug IP cores.
- Instantiate an ICON core in your design that is used to connect the other legacy ChipScope Pro debug IP cores to the JTAG chain infrastructure.
Important: Make sure that the
ICON and dbg_hub cores do
not use the same JTAG user scan chain; doing so produces errors during write_bitstream DRC checking. To change the JTAG user scan chain of the dbg_hub core:
- Open the synthesized design.
- In the Netlist window, select the dbg_hub core.
- In the Cell Properties window, select the Debug Core Options.
- Modify the
C_USER_SCAN_CHAINproperty value to a value that does not conflict with theICONcores in your design.