- Open the MHS file for the XPS design in a text editor.
- Determine which interfaces are used on MicroBlaze. Search the MHS file
for
BUS_INTERFACE ILMB, BUS_INTERFACE DLMB, BUS_INTERFACE M_AXI_DP, BUS_INTERFACE M_AXI_DC, BUS_INTERFACE M_AXI_IC, BUS_INTERFACE DEBUG, BUS_INTERFACE INTERRUPT.Typically, MicroBlaze designs built by the Base System Builder (BSB) contain LMB interfaces for local block RAM.
MicroBlaze Data Port interface (for slave registers, such as AXI GPIO), debug interface (using MDM with or without UART based upon the
C_USE_UARTparameter in MDM IP), and interrupt support (using theAXI_INTCslave IP). In addition, BSB adds clock and reset support with theclock_generatorandproc_sys_resetIP.More complex interfaces use the MicroBlaze Instruction Cache Port and MicroBlaze Data Cache Port. Typically, these interfaces are used for high performance portions of the design that use
AXI MIGorAXI block RAM(AXI4 slaves). TheC_CACHE_BYTE_SIZEandC_DCACHE_BYTE_SIZEparameters determine the size of caches for the MicroBlaze MHS instance. - Refer to the table below and set MicroBlaze Block Automation, based on the interfaces in the MHS file for the MicroBlaze instance.
| Interface | Exists | Does Not Exist |
|---|---|---|
| BUS_INTERFACE ILMB BUS_INTERFACE DLMB |
Local Memory: Select KB size based upon C_BASEADDR/C_HIGHADDR for LMB BRAM if a CNTLR instance is in the MHS |
Local Memory: None |
| BUS_INTERFACE DEBUG |
C_USE_UART = 0 on MDM instance in MHS Debug Module: Debug Only C_USE_UART = 1 on MDM instance in MHS Debug Module: Debug and UART |
Debug Module: None |
| BUS_INTERFACE M_AXI_DP | Peripheral AXI Port: Checked | Peripheral AXI Port: Disabled |
| BUS_INTERFACE M_AXI_IC BUS_INTERFACE M_AXI_DC |
Cache Configuration: Select cache size in KB based upon C_CACHE_BYTE_SIZE or C_DCACHE_BYTE_SIZE for MicroBlaze Instance in MHS |
Cache Configuration: None |
| BUS_INTERFACE INTERRUPT | Interrupt Controller: Checked | Interrupt Controller: Unchecked |