You can also accomplish XPS IP instantiation into the IP integrator by using the
create_bd_cell Tcl command with the appropriate options.
Some IP from the ISE Design Suite IP catalog were modified to suit the embedded design needs and delivered in the XPS IP catalog. With unification of the IP catalogs, certain IP transitions require additional attention.
- AXI 7 series DDRx to MIG
- Block RAM to Block Memory Generator
- Clock Generator to Clocking Wizard
- AXI Interconnect is used to interconnect the IP and processor
- Debug IP: Most of the Debug IP are available in the Vivado Design
Suite tools, just as in XPS. The available debug IP are:
- AXI Performance Monitor
- Vivado Integrated Logic Analyzer (ILA)
- Virtual I/O
- MicroBlaze Debug Module