The CSI-2 RX Subsystem core latency is the time from the start-of-transmission (SoT) pattern on the serial lines to the tvalid signal assertion at CSI-2 RX Subsystem output. This includes the D-PHY latency, MIPI RX Controller latency and VFB latency (if the Video Format Bridge is included in the subsystem).
This Figure represents the latency calculation for the subsystem.
