Hardware Validation - 5.1 English

The MIPI CSI-2 RX Subsystem is tested in hardware for functionality, performance, and reliability using Xilinx® evaluation platforms. The MIPI CSI-2 RX Subsystem verification test suites for all possible modules are continuously being updated to increase test coverage across the range of possible parameters for each individual module.

A series of MIPI CSI-2 RX Subsystem test scenarios are validated using the Xilinx development boards listed in Table: Xilinx Development Board . These boards permit the prototyping of system designs where the MIPI CSI-2 RX Subsystem processes different short/long packets received on serial lines.

Table A-1: Xilinx Development Board
Target Family	Evaluation Board	Characterization Board
Zynq® UltraScale+™ MPSoC	ZCU102	N/A
Zynq-7000 SoC	ZC702	N/A
Spartan-7 FPGA	SP701	N/A
Versal® ACAP	VCK190	N/A

Xilinx 7 series FPGAs do not have a native MIPI IOB support. You will have to target either the HR bank I/O or the HP bank I/O for the MIPI IP implementation. For more information on MIPI IOB compliant solution and guidance, refer D-PHY Solutions (XAPP894) [Ref 15] .

A series of interoperability test scenarios listed in Table: Interoperability Testing UltraScale+ Device and Table: Interoperability Testing with Xilinx 7 Series FPGAs are validated using different core configurations and resolutions. All ZCU102 designs use the native MIPI I/O available in the UltraScale+ ™ FPGA.

Note: Sony IMX274 tested in continuous & non-continuous clock mode. All other sensors operating in continuous clock mode.

Table A-2: Interoperability Testing UltraScale+ Device
Sensor	Board/Device	Tested Configuration	Resolution
Omnivision OV13850	ZCU102/xczu9eg-ffvb1156-2-e	1200 Mb/s 1, 2, 4 Lanes RAW8, RAW10, RAW12	480p@60fps 720p@60fps 1080p@60fps 4k@30fps
Sony IMX274	ZCU102/xczu9eg-ffvb1156-2-e	1440 Mb/s 4 Lanes RAW10, RAW12	All supported modes by sensor
Sony IMX224	ZCU102/xczu9eg-ffvb1156-2-e	149 Mb/s, 594 Mb/s 1, 2, 4 Lanes RAW10, RAW12	All-pixel (QVGA) and Window cropping modes
ON Semi AR0330	ZCU102/xczu9eg-ffvb1156-2-e	490 Mb/s 4 Lanes RAW10	480p@60fps 720p@60fps 1080p@60fps
Sony IMX334	ZCU102/xczu9eg-ffvg1156-2-e	1782 Mb/s 4 Lanes RAW12	4K@30fps
Sony IMX412	ZCU102/xczu9eg-ffvb1156-2-e	2100 Mb/s 4 Lanes RAW10	4K@60fps

All Xilinx 7 series FPGA interop designs use the external Meticom (MC20901) based solution which implements MIPI D-PHY I/O.

Table A-3: Interoperability Testing with Xilinx 7 Series FPGAs
Sensor	Board/Device	Tested Configuration	Calibration Mode	Resolution
Sony IMX274	ZC702/ xc7z020clg484-1	576 Mb/s 4 Lanes RAW10	Auto Enable 300 MHz clock for IDELAYCTRL=false	1080p@60fps
Sony IMX274	ZC702/ xc7z020clg484-1	1152 Mb/s 2 Lanes RAW10	Auto Enable 300 MHz clock for IDELAYCTRL=true	1080p@60fps
ON Semi AR0330	KC705/xc7k325tffg900-2	490 Mb/s 4 Lanes RAW10	None	480p@60fps 720p@60fps 1080p@60fps 2304x1296@60fps
ON Semi AR0330	KC705/xc7k325tffg900-2	588 Mb/s 4 Lanes RAW12	None	1080p@60fps 2304x1296@60fps
ON Semi AR0330	ZC702/ xc7z020clg484-1	490 Mb/s 4 Lanes RAW10	None	480p@60fps

All Xilinx 7 series FPGA loopback designs use the XM107 [Ref 19] loopback card.

Table A-4: Loopback Testing with Xilinx 7 Series FPGA
Board/Device	Line Rate	Lanes	Calibration Mode	Clock Selection (C_EN_CLK300M)
AC701/ xc7a200tfbg676-2	1250	4	Auto	False
KC705/ xc7k325tffg900-2	1250	4	Auto	False
VC709/ xc7vx690tffg1761-2	1250	4	Auto	False
ZC702/ xc7z020clg484-1	928	4	Auto	True
ZC706/ xc7z045ffg900-2	1250	4	Auto	True

Following board guidelines such as equal trace lengths helps to achieve higher line rates. For PCB guidelines see the UltraScale Architecture PCB Design User Guide (UG583) [Ref 17] .