Clock Lane Information Register - 5.1 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)
Document ID
PG232
Release Date
2022-04-26
Version
5.1 English

The Clock Lane Information register is described in Table: Clock Lane Information Register (0x3C) . The Stop state is captured in this register.

Table 2-28: Clock Lane Information Register (0x3C)

Bits

Name

Reset Value

Access

Description

31–2

Reserved

N/A

N/A

Reserved

1

Stop state

0x0

R

Stop state on clock lane

0

Reserved

N/A

N/A

Reserved