General Checks - 5.1 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

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5.1 English

Ensure MIPI DPHY and MIPI CSI-2 RX Controller cores are in the enable state by reading the registers.

Ensure Incorrect Lane Configuration is not set in the MIPI CSI-2 RX Controller Interrupt Status register.

Ensure that the output AXI4-Stream bandwidth is high enough to meet throughput demand.

Ensure line buffer full condition is not set in the MIPI CSI-2 RX Controller Interrupt Status register. Core setting this bit implies that the input data rate is higher than the output data rate. Consider either decreasing input data rate (DPHY Line rate) or increase output data rate (Select appropriate output pixel per Clock: Single, Dual, Quad).

Following MIPI CSI-2 RX Controller registers can be monitored to confirm reception of data packets

° Packet count in Core Status register

° Data type and Byte count in Image Information registers

° Frame received bit in Interrupt Status register

No packets received by MIPI CSI-2 Subsystem

° Possible causes:

- No packets received at MIPI DPHY level itself

- Frame end packets not received or not passed the ECC checks at MIPI CSI-2 RX Subsystem level

° Debug instructions:

- Verify MIPI DPHY packet count registers. If the packet counts at MIPI DPHY level are not getting reported, debug connections/paths from source to MIPI DPHY Input

- Verify MIPI CSI-2 RX Controller interrupt status register to see if any ECC errors getting reported. If there is frequent ECC 2-bit error getting reported means some of the packets are not getting processed by MIPI CSI-2 RX Controller.

Packets received by MIPI CSI-2 Subsystem with PPI Level Errors (like SoT Error, SoT sync Error) and/or Controller level errors (like ECC 1-bit, ECC 2-bit, CRC).

° Possible causes:

- Lane position mismatch between source (sensor) and MIPI CSI-2 RX Subsystem.

- Noise detected by MIPI DPHY as a valid packet.

° Debug instructions:

- Verify that the lane positions of the source (sensor) and the MIPI CSI-2 RX Subsystem are matching. Lane0 holds first byte of the packet, Lane1 holds the next byte and so on.

- Verify that sensor TX output timing. If it does not meet MIPI specification, adjust the MIPI D-PHY RX HS_SETTLE setting. When subsequently processed by the MIPI CSI-2 RX Controller, these packets are reported as erroneous packets. Increase the HS_SETTLE value either through the MIPI DPHY registers or through the C_HS_SETTLE_NS parameter (hidden) available in MIPI CSI-2 RX Subsystem.

For more debug information on MIPI DPHY, refer to the MIPI D-PHY LogiCORE IP Product Guide ( PG202 ) [Ref 3] . To debug further, capture the PPI signals using the Vivado ® Logic analyzer and confirm the bytes received through source (sensor) are as expected for short and long packets.