The Lane<n> Information register, where n is 0, 1, 2 or 3, is described in Table: Lane 0, 1, 2, 3 Information Register (0x40, 0x44, 0x48, 0x4C) and provides the status of the <n> data lane. This register is reset when any write to the Protocol Configuration register is detected, irrespective of whether the Protocol Configuration register contents are updated or not.
|
Bits |
Name |
Reset Value |
Access |
Description (2) |
|---|---|---|---|---|
|
31–6 |
Reserved |
N/A |
N/A |
Reserved |
|
5 |
Stop state |
0x0 |
RO |
Detection of stop state |
|
4 |
Reserved |
N/A |
N/A |
Reserved |
|
3 |
Reserved |
N/A |
N/A |
Reserved |
|
2 |
skewcalhs |
0x0 |
R |
Indicates the deskew reception |
|
1 |
SoT error |
0x0 |
R |
Detection of SoT Error |
|
0 |
SoT Sync error |
0x0 |
R |
Detection of SoT Synchronization Error |
|
Notes: 1. Lane Information registers are present only for the maximum defined number of lanes. Reads to others registers gives 0x0. |
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