Lane<n> Information Registers - 5.1 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2022-04-26
Version
5.1 English

The Lane<n> Information register, where n is 0, 1, 2 or 3, is described in Table: Lane 0, 1, 2, 3 Information Register (0x40, 0x44, 0x48, 0x4C) and provides the status of the <n> data lane. This register is reset when any write to the Protocol Configuration register is detected, irrespective of whether the Protocol Configuration register contents are updated or not.

Table 2-29: Lane 0, 1, 2, 3 Information Register (0x40, 0x44, 0x48, 0x4C)

Bits

Name

Reset Value

Access

Description (2)

31–6

Reserved

N/A

N/A

Reserved

5

Stop state

0x0

RO

Detection of stop state

4

Reserved

N/A

N/A

Reserved

3

Reserved

N/A

N/A

Reserved

2

skewcalhs

0x0

R

Indicates the deskew reception

1

SoT error

0x0

R

Detection of SoT Error

0

SoT Sync error

0x0

R

Detection of SoT Synchronization Error

Notes:

1. Lane Information registers are present only for the maximum defined number of lanes. Reads to others registers gives 0x0.

2. All bits are reported through the PPI.