Video clock calculation example - 5.1 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

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5.1 English

For a MIPI interface with 600Mb/s per lane, 4 lanes, single pixel mode design, processing YUV420 8-bit data, the minimum required video clock is (600*4)/(1*8) or higher, where 8 is the number of bits in one 8-bit YUV420 pixel.

video_aclk1(Mhz) = 600*4/(4*8) = 75Mhz
video_aclk2(Mhz) = 600*4/(1*8) = 300Mhz

The final video clock is:

video_aclk(Mhz) = max{75Mhz,300Mhz} = 300Mhz

Note: Due to the internal data path architecture of the pixel processing the minimum supported data type for line rates greater than 1500 Mb/s is RAW8. RAW6 and RAW7 data types are not supported for line rates greater than 1500 Mb/s.