The Interrupt Status register (ISR) is described in Table: Interrupt Status Register (0x24) and captures the error and status information for the core.
Bits |
Name |
Reset
|
Access (1) |
Description |
---|---|---|---|---|
31 |
Frame Received |
0x0 |
R/W1C |
Asserted when the Frame End (FE) short packet is received for the current frame |
30 |
VCX Frame Error |
0x0 |
RO |
Asserted when the VCX Frame error is detected |
29 |
RX_Skewcalhs |
0x0 |
R/W1C |
Asserted when rxskewcalhs is detected. |
28 |
YUV420 WC Error |
0x0 |
R/W1C |
Asserted when the user-configured YUV420 word count value is less than the actual Y-line word count of the incoming data, which results in an internal buffer full condition. Note: Ensure the Y-line word count of the incoming data is at least 8 bytes less than the value configured in GUI to avoid this flag. |
27 |
Pending write in internal FIFO |
0x0 |
R/W1C |
Indicates internal FIFO has insufficient clocks to process the packet. This happens in non-continuous clock mode if there are insufficient clocks to completely write the PPI data to internal FIFO. To resolve this, the user needs to increase the Tclk-post parameter in the transmitter. Incase this bit is seen set by default, write 1 to clear this bit after the rxbyteclkhs starts toggling. |
26–23 |
Reserved |
N/A |
N/A |
N/A |
22 |
Word Count (WC) corruption |
0x0 |
R/W1C |
Asserted when WC field of packet header corrupted and core receives less bytes than indicated in WC field. Such a case can occur only where more than 2-bits of header are corrupted which ECC algorithm cannot report and the corruption is such that the ECC algorithm reports a higher Word Count (WC) value as part of ECC correction. In such case core limits processing of the packet on reduced number of bytes received through PPI interface. |
21 |
Incorrect lane configuration |
0x0 |
R/W1C |
Asserted when Active lanes is greater than Maximum lanes in the protocol configuration register |
20 |
Short packet FIFO full |
0x0 |
R/W1C |
Active-High signal asserted when the short packet FIFO full condition detected |
19 |
Short packet FIFO not empty |
0x0 |
R/W1C |
Active-High signal asserted when short packet FIFO not empty condition detected |
18 |
Stream line buffer full |
0x0 |
R/W1C |
Asserts when the line buffer is full (2) |
17 |
Stop state |
0x0 |
R/W1C |
Active-High signal indicates that the lane module is currently in Stop state (3) |
16 |
Reserved |
N/A |
N/A |
N/A |
15 |
Reserved |
N/A |
N/A |
N/A |
14 |
Reserved |
N/A |
N/A |
N/A |
13 |
SoT error
|
0x0 |
R/W1C |
Indicates Start-of-Transmission (SoT) error detected (3) |
12 |
SoT sync error
|
0x0 |
R/W1C |
Indicates SoT synchronization completely failed (3) |
11 |
ECC 2-bit error
|
0x0 |
R/W1C |
Asserted when an ECC syndrome is computed and two bit errors detected in the received packet header |
10 |
ECC 1-bit error
(ErrEccCorrected) |
0x0 |
R/W1C |
Asserted when an ECC syndrome was computed and a single bit error in the packet header was detected and corrected |
9 |
CRC error
|
0x0 |
R/W1C |
Asserted when the computed CRC code is different from the received CRC code |
8 |
Unsupported Data Type
|
0x0 |
R/W1C |
Asserted when a packet header is decoded with an unrecognized or not implemented data ID |
7 |
Frame synchronization
|
0x0 |
R/W1C |
Asserted when an FE is not paired with a Frame Start (FS) on the same virtual channel (4) |
6 |
Frame level error for VC3
|
0x0 |
R/W1C |
Asserted after an FE when the data payload received between FS and FE contains errors.
|
5 |
Frame synchronization
|
0x0 |
R/W1C |
Asserted when an FE is not paired with a FS on the same virtual channel (4) |
4 |
Frame level error for VC2
|
0x0 |
R/W1C |
Asserted after an FE when the data payload received between FS and FE contains errors.
|
3 |
Frame synchronization
|
0x0 |
R/W1C |
Asserted when an FE is not paired with a FS on the same virtual channel (4) |
2 |
Frame level error for VC1
|
0x0 |
R/W1C |
Asserted after an FE when the data payload received between FS and FE contains errors.
|
1 |
Frame synchronization
|
0x0 |
R/W1C |
Asserted when a FE is not paired with a FS on the same virtual channel (4) |
0 |
Frame level error for VC0
|
0x0 |
R/W1C |
Asserted after an FE when the data payload received between FS and FE contains errors.
|
Notes: 2. In a line buffer full condition, reset the core using the external reset, video_aresetn. 4. An ErrSotSyncHS error also generates this error signal. 5. Short packet and line buffer FIFO full conditions take a few clock periods to reflect in the register clock domain from the core clock domain due to Clock Domain Crossing (CDC) blocks. 6. All PPI signals captured in the ISR take a few clock periods to reflect in the register clock domain from the PPI clock domain due to CDC blocks. 7. Frame level errors due to ErrSotSyncHS are mapped to the recent VC processed by the ECC block of the core. 8. Set conditions take priority over the reset conditions for the ISR bits. 9. Signal names in brackets are defined in the MIPI Alliance Standard for Camera Serial Interface CSI-2 [Ref 1] . |
Set Condition(s) |
Set by the core when the line buffer storing pixel data is full. |
Reset Sequence |
Write 1 to clear this bit. |
Priority |
Set condition takes priority over reset sequence. |
Impact |
Core reports this condition on stream interface using an error indication on the TUSER[1] port if a partial packet is being written to line buffer. Because PPI does not allow back pressure, you need to ensure that this condition does not occur. |
Set Condition(s) |
Set by the core when the condition for the corresponding signal as defined in the MIPI CSI-2 specification [Ref 1] is seen, reported through the PPI interface. |
Reset Sequence |
Write 1 to clear this bit. |
Priority |
Set condition takes priority over reset sequence. |
Impact |
Current packet being processed does not have any impact. |
Set Condition(s) |
Set by the core when the current packet being processed has Start-of-Transmission (SoT) Error reported through PPI Interface. |
Reset Sequence |
Write 1 to clear this bit. |
Priority |
Set condition takes priority over reset sequence. |
Impact |
Current packet under process does not have any impact as synchronization is still achieved. This is considered to be a “soft error” in the leader sequence and confidence in the payload data is reduced. |
Set Condition(s) |
Set by the core when current packet being processed has Start-of-Transmission Synchronization Error reported through PPI interface. |
Reset Sequence |
Write 1 to clear this bit. |
Priority |
Set condition takes priority over reset sequence. |
Impact |
The current packet being processed is not processed further. The core waits for the next packet to process. |
Set Condition(s) |
Set by the core when an ECC syndrome was computed and two bit-errors are detected in the received Packet Header. |
Reset Sequence |
Write 1 to clear this bit. |
Priority |
Set condition takes priority over reset sequence. |
Impact |
Current packet being processed is not processed further as WC is not usable, and thus the packet end cannot be estimated.The core waits for the next packet to process. |
Set Condition(s) |
Set by the core when an ECC syndrome was computed and a single bit-error in the Packet Header was detected and corrected. |
Reset Sequence |
Write 1 to clear this bit. |
Priority |
Set condition takes priority over reset sequence. |
Impact |
Current packet being processed does not have any impact. |
Set Condition(s) |
Set by the core when the computed CRC code is different than the received CRC code. |
Reset Sequence |
Write 1 to clear this bit. |
Priority |
Set condition takes priority over reset sequence. |
Impact |
Current packet being processed does not have any impact, but the payload might be corrupted. |
Set Condition(s) |
Set by the core when a Packet Header is decoded with an unrecognized or un-implemented data ID. |
Reset Sequence |
Write 1 to clear this bit. |
Priority |
Set condition takes priority over reset sequence. |
Impact |
Current packet being processed is not processed further. The core waits for the next packet to process. |
Source |
Impact on Packet Processing |
---|---|
FS followed by FS |
Processed |
ErrEccDouble |
Not processed |
FE followed FE |
Processed |
ErrSotSyncHS |
Not processed |
Tables 2-13 to 2-24 provide detailed information about the bits in Table: Interrupt Status Register (0x24) .