Table: Vivado IDE Parameter to User Parameter Relationship
shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console).
Table 4-1:
Vivado IDE Parameter to User Parameter Relationship
|
Vivado IDE Parameter
|
User Parameter
|
Default Value
|
|
Pixel Format
|
CMN_PXL_FORMAT
|
RAW8
|
|
YUV420 word count
|
YUV420_BUF_DPTH
|
128
|
|
Serial Data Lanes
|
CMN_NUM_LANES
|
1
|
|
Allowed VC
|
CMN_VC
|
All
|
|
Pixels Per Clock
|
CMN_NUM_PIXELS
|
1
|
|
Include video Format Bridge (VFB)
|
CMN_INC_VFB
|
True
|
|
Support CSI Spec V2_0
|
C_EN_CSI_V2_0
|
False
|
|
Support VCX Feature
|
C_EN_VCX
|
False
|
|
Line Rate (Mb/s)
|
DPY_LINE_RATE
|
1000
|
|
D-PHY Register Interface
|
DPY_EN_REG_IF
|
False
|
|
Calibration Mode
|
C_CAL_MODE
|
None
|
|
IDELAY Tap Value
|
C_IDLY_TAP
|
1
|
|
External IDELAY tap loading
|
C_EN_EXT_TAP
|
False
|
|
Include IDELAYCTRL in Core
|
C_SHARE_IDLYCTRL
|
False
|
|
Enable 300 MHZ Clock for IDELAYCTRL
|
C_EN_CLK300M
|
False
|
|
Embedded non-image Interface
|
CSI_EMB_NON_IMG
|
False
|
|
Line Buffer Depth
|
CSI_BUF_DEPTH
|
2048
|
|
Enable CRC
|
C_CSI_EN_CRC
|
True
|
|
Enable Active Lanes
|
C_CSI_EN_ACTIVELANES
|
False
|
|
Shared Logic
|
Support Level
|
0
|
|
HP IO Bank Selection
|
HP_IO_BANK_SELECTION
|
Value based on part selected.
|
|
Clock Lane
|
CLK_LANE_IO_LOC
|
Value based on part selected
|
|
Data Lane0
|
DATA_LANE0_IO_LOC
|
Value based on part selected
|
|
Data Lane1
|
DATA_LANE1_IO_LOC
|
Value based on part selected
|
|
Data Lane2
|
DATA_LANE2_IO_LOC
|
Value based on part selected
|
|
Data Lane3
|
DATA_LANE3_IO_LOC
|
Value based on part selected
|
|
HS_SETTLE Parameter (ns)
|
C_HS_SETTLE_NS
|
145
Note:
Hidden parameter which can be
used to set HS_SETTLE value. Can be set
through Tcl flow.
|
|
Filter User Defined data types
|
C_CSI_FILTER_USERDATATYPE
|
False
|
|
Target Board
|
C_EXDES_BOARD
|
ZCU102
|
|
FMC Model
|
C_EXDES_FMC
|
LI-IMX274MIPI-FMC V1.0 Single Sensor
|
|
Design Topology
|
C_EXDES_CONFIG
|
MIPI_Video_Pipe_Camera_to_Display
|
|
TDATA Width
|
AXIS_TDATA_WIDTH
|
32
|
|
TDEST Width
|
AXIS_TDEST_WIDTH
|
4
|
|
TUSER Width (CSI-2 options)
|
AXIS_TUSER_WIDTH
|
96
|
|
TUSER Width (VFB options)
|
VFB_TU_WIDTH
|
1
|