Features - 5.1 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
Release Date
5.1 English

Support for 1 to 4 D-PHY lanes

Line rates ranging from 80 to 3200 Mb/s

Multiple Data Type support (RAW, RGB, YUV)

Filtering based on Virtual Channel Identifier

Support for 1, 2, or 4 pixels per clock at the output as defined in the Xilinx AXI4-Stream Video IP and System Design Guide (UG934) [Ref 2] format

AXI4-Lite interface for register access to configure different subsystem options

Dynamic selection of active lanes within the configured lanes during subsystem generation.

Interrupt generation to indicate subsystem status information

Internal D-PHY allows direct connection to image sources

Support for MIPI CSI-2 standard v2.0 features such as VCX, RAW16, and RAW20

IP Facts Table

Subsystem Specifics

Supported Device Family (1)


Versal ® ACAP
Zynq ® UltraScale+ MPSoC

Zynq ® UltraScale+ RFSoC

Zynq ® -7000 SoC
7 series

Supported User Interfaces

AXI4-Lite, AXI4-Stream


Performance and Resource Utilization web page

Provided with Subsystem

Design Files

Encrypted RTL

Example Design

Vivado IP Integrator

Test Bench

Not Provided

Constraints File


Simulation Model

Not Provided

S/W Driver

Standalone and Linux

Tested Design Flows (3)

Design Entry

Vivado® Design Suite


For supported simulators, see the
Xilinx Design Tools: Release Notes Guide .


Vivado Synthesis


Release Notes and Known Issues

Master Answer Record: 65242

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page


1. For a complete list of supported devices, see the Vivado IP catalog.

2. Standalone driver details can be found in the Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver support information is available from the Xilinx Wiki page .

3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide .