Using the CLOCK_DELAY_GROUP Constraint on Several Clock Nets - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

You can use the CLOCK_DELAY_GROUP constraint to match the insertion delay of multiple, related clock networks driven by different clock buffers. This constraint is commonly used to minimize skew on synchronous CDC timing paths between clocks originating from the same MMCM, PLL, or GT source. You must set the CLOCK_DELAY_GROUP constraint on the net segment directly connected to the clock buffer. The following example shows the clk1_net and clk2_net clock nets, which are directly driven by the clock buffers:

set_property CLOCK_DELAY_GROUP grp12 [get_nets {clk1_net clk2_net}]