Balanced Utilization of High and Low Fanout Clocks - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
Release Date
2022.1 English

UltraScale devices support more clocks than previous Xilinx device families. This enables a wide range of clocking utilization scenarios, such as the following:

  • 24 clocks or less

    Unless conflicting user constraints exist, all clocks can be treated as high fanout clocks without risking placement or routing contention.

  • Almost 300 clocks

    For a design that targets a device with 6 clock region rows and includes only low fanout clocks with each clock included in 3 clock regions at most, the following clocks are required: 6 rows x 2 clock windows per row x 24 clocks per region = 288 clocks.

Low fanout clock windows do not have a fixed size but are usually between 1 and 3 clock regions. High fanout clocks rarely span the entire device or an entire SLR.

The following method shows how to balance high fanout clocks and low fanout clocks, assuming that a few low fanout clocks come from I/O interfaces and most from GT interfaces. You can apply the same method for each SSI technology device SLR.

  • High fanout clocks
    • Up to 12 for monolithic devices
    • Up to 24 for SSI technology devices (assuming some high fanout clocks are only present in 1 SLR)
  • Low fanout clocks
    • Up to 12 plus 8 per GT utilized Quad
    • Alternatively, up to 12 plus 6 per GT interface (group of GT channels that share the RXUSRCLK and TXUSRCLK)