Clock Interaction Report - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
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2022.1 English

The Clock Interaction report provides a high-level summary of how two clocks are timed together:

  • Do the two clocks have a common primary clock? When clocks are properly defined, all clocks that originate from the same source in the design share the same primary clock.
  • Do the two clocks have a common period? This shows in the setup or hold path requirement column (unexpandable), when the timing engine cannot determine the most pessimistic setup or hold relationship.
  • Are the paths between the two clocks partially or completely covered by clock groups or timing exception constraints?
  • Is the setup path requirement between the two clocks very tight? This can happen, when two clocks are synchronous, but their period is not specified as an exact multiple (for example, due to rounding off). Over multiple clock cycles, the edges could drift apart, causing the worst case timing requirement to be very tight.