Super Logic Region (SLR) - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

A super logic region (SLR) is a single device die slice contained in an SSI technology device. Each SLR contains a subset of device resources, such as CLBs, block RAMs, DSP tiles, and GTs, with a similar structure to non-SSI devices.

Multiple SLR components are stacked vertically and connected through an interposer to create an SSI technology device. The bottom SLR is SLR0, and subsequent SLR components are named incrementally as they ascend vertically.

For example, the XC7V2000T device includes four SLR components. The bottom SLR is SLR0, the SLR directly above SLR0 is SLR1, the SLR directly above SLR1 is SLR2, and the top SLR is SLR3.

Note: The Xilinx tools clearly identify SLR components in the graphical user interface (GUI) and in reports.