Pin Assignment - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

Good pinout selection leads to good design logic placement, shorter routes, reduced power consumption, and improved performance. Good pinout selection is especially important for large devices, because a pinout that is spread out can cause related signals to span longer distances. For more information, see this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).