Post-Synthesis and Post-Logic Optimization - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

Estimated net delays are close to the best possible placement for all paths. To fix violating paths try the following:

  • Change the RTL.
  • Use different synthesis options.
  • Add timing exceptions such as multicycle paths, if appropriate and safe for the functionality in hardware.