Using Incremental Implementation Flows - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

In the Vivado Design Suite, you can use incremental implementation to reuse existing placement and routing data, which reduces implementation compile time and produces more predictable results. When working with designs that have 95% or higher reuse, incremental place and route typically achieves at least a twofold improvement over normal place and route compile times while maintaining the WNS of the reference run. For more information, see this link in the Vivado Design Suite User Guide: Implementation (UG904).

Note: For further improvement in compile times and QoR, you can also use incremental synthesis.