Constraining Input and Output Ports - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

In addition to specifying the location and I/O standard for each port of the design, input and output delay constraints must be specified to describe the timing of external paths to/from the interface of the device. These delays are defined relative to a clock that is usually also generated on the board and enters the device. In some cases, the delays must be defined related to a virtual clock when the I/O path is related to a clock that has a waveform different from the board clock.

Important: I/O delays can only be constrained for interfaces using I/O logic, such as ISERDES/OSERDES/IDDR/ODDR/IOB registers or fabric. For guidance on component mode timing, see Designing Using SelectIO Interface Component Primitives (XAPP1324). For high-speed I/O interfaces created using UltraScale device SelectIO native mode, see Answer Record 68618.