Single Quad vs. Multi-Quad Interface - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

In a multi-channel interface, a master channel can generate [RT]XUSRCLK[2] for all the GT*CHANNELs of the interface. If a multi-channel interface spans multiple quads, the maximum allowed distance for a GT*CHANNEL from the reference clock source is 2 clock regions above and below.

The following figure shows a multi-quad interface. The GT*CHANNELs are marked in yellow, the TXUSRCLK is highlighted in blue, and the TXUSRCLK2 is highlighted in red. The BUFG_GTs driving both TXUSRCLK and TXUSRCLK2 are located in the center quad and are marked in blue and red.

Figure 1. TXUSRCLK/TXUSRCLK2 Clock Routing for a Multi-Quad Interface

If the GT interface is contained within a single Quad, the placer treats the BUFG_GT clocks as local clocks. In this case, the placer attempts to place the BUFG_GT clock loads in the clock regions horizontally adjacent to the BUFG_GT, starting with the clock region that contains the BUFG_GT and potentially using up to half the width of the device.

To override the placer regional clock constraint, assign any of the BUFG_GT clock loads to a Pblock. The following figure shows a single-quad interface. The GT*CHANNELs are marked in yellow, the TXUSRCLK is highlighted in blue, and the TXUSRCLK2 is highlighted in red. All the TXUSRCLK2 loads are placed in the same clock region as the GT*CHANNELs.

Figure 2. TXUSRCLK/TXUSRCLK2 Clock Routing for a Single-Quad Interface