Board Design Tips - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

When designing a board, it is important to consider which interfaces and pins will assist with debug capability beyond configuration. For example, Xilinx recommends that you ensure the JTAG interface is accessible even when the interface is not the primary configuration mode. The JTAG interface allows you to check the device ID and device DNA information, and you can use the interface to enable indirect flash programming solutions during prototyping.

In addition, signals such as the INIT_B and DONE are critical for device configuration debug. The INIT_B signal has multiple functions. It indicates completion of initialization at power-up and can indicate when a CRC error is encountered. Xilinx recommends that you connect the INIT_B and DONE signals to light-emitting diodes (LEDs) using LED drivers and pull-ups.

For recommended pull-up values, see the configuration user guide for your device:

  • 7 Series FPGAs Configuration User Guide (UG470)
  • UltraScale Architecture Configuration User Guide (UG570)

To identify and check recommended board-level pin connections, see the schematic checklists:

  • 7 Series Schematic Review Recommendations (XMP277)
  • Kintex UltraScale and Virtex UltraScale FPGAs Schematic Review Checklist (XTP344)
  • UltraScale+ FPGAs and Zynq Ultrascale+ Devices Schematic Review Checklist (XTP427)