Thermal Solution Considerations - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

When considering the power estimation of a design, understanding the efficiency of the thermal solution is crucial. The lower the junction temperature, the lower the static power of a design.

Xilinx recommends using lidless packaging if it is available for your device. Lidless packaging offers a more efficient thermal solution and allows direct contact with the heat source, removing a thermal interface material (TIM) layer. Xilinx lidded and lidless parts have the same handling and manufacturing requirements. The following figure compares the heat sink application for a lidded and lidless device.

Thermal Tip: Xilinx recommends between 20 and 50 pound-force per square inch (PSI) for the heat sink, which ensures the smallest bond line thickness (BLT), and recommends using 4-hole mounting to ensure even pressure for both lidded and lidless devices. For more information on lidless techniques, see Mechanical and Thermal Design Guidelines for Lidless Flip-Chip Packages (XAPP1301).
Figure 1. Heat Sink Example

Xilinx also recommends thermal simulation to ensure that there is adequate margin and accurate power estimation. In the XPE, you have control over the following thermal settings:
Junction Temperature Tj
You can override this setting to a desired junction temperature to match your thermal simulation. If you are not running a thermal simulation, set the junction temperature to the worst case.
Effective ΘJA
Describes the thermal efficiency of a thermal solution, the units are measured in degrees Celsius per watt (°C/W). For example, an ΘJA of 2.1°C/W means that for every watt dissipated in the device, the junction temperature increases by 2.1°C. For a 10W design, the increase is 21°C above the ambient temperature.
Note: You can obtain the ΘJA through thermal simulation using the following formula:
ΘJa = (Tj – Ta)/ PowerDissipated

The following figure shows the recommended flow for thermal validation.

Figure 2. Recommended Thermal Validation Flow
Page-1 Rectangle.483 Power Estimation PowerEstimation Rectangle.3 Re-Evaluate Design or Thermal Solution Re-Evaluate Design or Thermal Solution Rectangle.4 Thermal Simulation Tj < Tj max Thermal SimulationTj < Tj max Rectangle.6 Y Y Sheet.8 Standard Arrow.487 Sheet.11 Sheet.12 Standard Arrow.47 Rectangle.15 N N Sheet.16 X23525-111319 X23525-111319

After the junction temperature is within specification and sufficient margin is considered, the thermal solution is considered effective.

Thermal Tip: Add the results of the power estimation and thermal simulation to the Vivado design constraints. You can use the following XDC constraints, which you can export from the XPE, as described in the Xilinx Power Estimator User Guide (UG440) :
# Standard Constraints:
set_operating_conditions -process Maximum
set_operating_conditions -design_power_budget <value>
#If thermal simulation completed
set_operating_conditions -ambient_temp <value>
set_operating_conditions -thetaja <value>
#Else if no thermal simulation completed
set_operating_conditions -junction_temp <value>