High and Low Reuse Modes - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

If you use the incremental implementation flow without enabling automatic incremental implementation mode, the reuse level triggers one of the following reuse modes:

High Reuse Mode
High reuse mode is enabled when cell reuse is equal to or greater than 75%. This mode triggers incremental algorithms to be run and is the standard mode for incremental implementation.
Low Reuse Mode
Low reuse mode is enabled when cell reuse is less than 75%. This mode reuses the cell placement of certain cells but runs the default algorithms. This mode can be effective when targeting block placement of DSPs, BRAMs, or a hierarchical cell.