Gigabit Transceiver Output Pins in 7 Series Devices - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)

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2022.1 English

You can use a gigabit transceiver output pin (e.g., a recovered clock) as the primary clock root as shown in the following figure.

Figure 1. create_clock on a Primitive Pin

Constraint example:

create_clock -name txclk -period 6.667 [get_pins gt0/TXOUTCLK]
Note: For designs that target UltraScale™ and UltraScale+™ devices, Xilinx does not recommend defining a primary clock on the output of GTs, because GT clocks are automatically derived when the REFCLK input clocks are defined.