ILA Core Designs with High-Speed Clocks - 2022.1 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949)
Document ID
UG949
Release Date
2022-06-08
Version
2022.1 English

For designs with high-speed clocks, consider the following:

  • Limit the number and width of signals being debugged.
  • Pipeline the input probes to the ILA (C_INPUT_PIPE_STAGES), which enables extra levels of pipe stages.
Note: For designs with limited MMCM/BUFG availability, consider clocking the debug hub with the lowest clock frequency in the design instead of using the clock divider inside the debug hub.